The synchronous process library defines processes for the synchronous computational model. It is based on the synchronous library ForSyDe.Shallow.SynchronousLib.
- fifoDelaySY :: Signal [a] -> Signal (AbstExt a)
- finiteFifoDelaySY :: Int -> Signal [a] -> Signal (AbstExt a)
- memorySY :: Int -> Signal (Access a) -> Signal (AbstExt a)
- mergeSY :: Signal (AbstExt a) -> Signal (AbstExt a) -> Signal (AbstExt a)
- groupSY :: Int -> Signal a -> Signal (AbstExt (Vector a))
- counterSY :: (Enum a, Ord a) => a -> a -> Signal a
fifoDelaySY implements a synchronous model of a
FIFO with infinite size. The FIFOs take a list of values at each
event cycle and output one value. There is a delay of one cycle.
finiteFifoDelaySY implements a FIFO with finite
size. The FIFOs take a list of values at each event cycle and
output one value. There is a delay of one cycle.
memorySY implements a synchronous memory. It uses
access functions of the type 'Read adr' and 'Write adr value'.
mergeSY merges two input signals into a single
signal. The process has an internal buffer in order to prevent loss
of data. The process is deterministic and outputs events according
to their time tag. If there are two valid values at on both
signals. The value of the first signal is output first.
groupSY groups values into a vector of size n,
which takes n cycles. While the grouping takes place the output
from this process consists of absent values.