{-# OPTIONS_GHC -fno-warn-missing-fields #-}

-- |
-- Copyright  : Copyright (c) 2008, Emil Axelsson
-- License    : BSD3
-- Maintainer : Emil Axelsson <emax@chalmers.se>
-- Stability  : experimental
--
-- Lava interface to the Nangate45 library.
--
-- The data in this file is derived from Nangate's Open Cell Library,
-- and is subject to the license restrictions stated in
-- "Libs.Nangate45.LICENSE".
module Libs.Nangate45.Lava
  (
    -- * Library type
    Nangate45

    -- * Cells
  , and2_x1
  , and2_x2
  , and2_x4
  , buf_x1
  , buf_x16
  , buf_x2
  , buf_x32
  , buf_x4
  , buf_x8
  , fa_x1
  , fillcell_x1
  , fillcell_x16
  , fillcell_x2
  , fillcell_x32
  , fillcell_x4
  , fillcell_x8
  , ha_x1
  , inv_x1
  , inv_x16
  , inv_x2
  , inv_x32
  , inv_x4
  , inv_x8
  , logic0_x1
  , logic1_x1
  , nand2_x1
  , nand2_x2
  , nand2_x4
  , nor2_x1
  , nor2_x2
  , nor2_x4
  , or2_x1
  , or2_x2
  , or2_x4
  , xnor2_x1
  , xnor2_x2
  , xor2_x1
  , xor2_x2
  ) where

import Data.Hardware.Internal
import Lava.Internal
import Lava
import Analysis.Timing.Library
import Libs.Nangate45.Timing

import qualified Lava2000 as L
import qualified Lava2000.Arithmetic as L

data Nangate45 = AND2_X1 | AND2_X2 | AND2_X4 | BUF_X1 | BUF_X16 | BUF_X2 | BUF_X32 | BUF_X4 | BUF_X8 | FA_X1 | FILLCELL_X1 | FILLCELL_X16 | FILLCELL_X2 | FILLCELL_X32 | FILLCELL_X4 | FILLCELL_X8 | HA_X1 | INV_X1 | INV_X16 | INV_X2 | INV_X32 | INV_X4 | INV_X8 | LOGIC0_X1 | LOGIC1_X1 | NAND2_X1 | NAND2_X2 | NAND2_X4 | NOR2_X1 | NOR2_X2 | NOR2_X4 | OR2_X1 | OR2_X2 | OR2_X4 | XNOR2_X1 | XNOR2_X2 | XOR2_X1 | XOR2_X2
     deriving (Eq, Show)

instance CellLibrary Nangate45
  where
    numIns AND2_X1 = 2
    numIns AND2_X2 = 2
    numIns AND2_X4 = 2
    numIns BUF_X1 = 1
    numIns BUF_X16 = 1
    numIns BUF_X2 = 1
    numIns BUF_X32 = 1
    numIns BUF_X4 = 1
    numIns BUF_X8 = 1
    numIns FA_X1 = 3
    numIns FILLCELL_X1 = 0
    numIns FILLCELL_X16 = 0
    numIns FILLCELL_X2 = 0
    numIns FILLCELL_X32 = 0
    numIns FILLCELL_X4 = 0
    numIns FILLCELL_X8 = 0
    numIns HA_X1 = 2
    numIns INV_X1 = 1
    numIns INV_X16 = 1
    numIns INV_X2 = 1
    numIns INV_X32 = 1
    numIns INV_X4 = 1
    numIns INV_X8 = 1
    numIns LOGIC0_X1 = 0
    numIns LOGIC1_X1 = 0
    numIns NAND2_X1 = 2
    numIns NAND2_X2 = 2
    numIns NAND2_X4 = 2
    numIns NOR2_X1 = 2
    numIns NOR2_X2 = 2
    numIns NOR2_X4 = 2
    numIns OR2_X1 = 2
    numIns OR2_X2 = 2
    numIns OR2_X4 = 2
    numIns XNOR2_X1 = 2
    numIns XNOR2_X2 = 2
    numIns XOR2_X1 = 2
    numIns XOR2_X2 = 2

    numOuts AND2_X1 = 1
    numOuts AND2_X2 = 1
    numOuts AND2_X4 = 1
    numOuts BUF_X1 = 1
    numOuts BUF_X16 = 1
    numOuts BUF_X2 = 1
    numOuts BUF_X32 = 1
    numOuts BUF_X4 = 1
    numOuts BUF_X8 = 1
    numOuts FA_X1 = 2
    numOuts FILLCELL_X1 = 0
    numOuts FILLCELL_X16 = 0
    numOuts FILLCELL_X2 = 0
    numOuts FILLCELL_X32 = 0
    numOuts FILLCELL_X4 = 0
    numOuts FILLCELL_X8 = 0
    numOuts HA_X1 = 2
    numOuts INV_X1 = 1
    numOuts INV_X16 = 1
    numOuts INV_X2 = 1
    numOuts INV_X32 = 1
    numOuts INV_X4 = 1
    numOuts INV_X8 = 1
    numOuts LOGIC0_X1 = 1
    numOuts LOGIC1_X1 = 1
    numOuts NAND2_X1 = 1
    numOuts NAND2_X2 = 1
    numOuts NAND2_X4 = 1
    numOuts NOR2_X1 = 1
    numOuts NOR2_X2 = 1
    numOuts NOR2_X4 = 1
    numOuts OR2_X1 = 1
    numOuts OR2_X2 = 1
    numOuts OR2_X4 = 1
    numOuts XNOR2_X1 = 1
    numOuts XNOR2_X2 = 1
    numOuts XOR2_X1 = 1
    numOuts XOR2_X2 = 1

    inPinName AND2_X1 0 = "A1"
    inPinName AND2_X1 1 = "A2"
    inPinName AND2_X2 0 = "A1"
    inPinName AND2_X2 1 = "A2"
    inPinName AND2_X4 0 = "A1"
    inPinName AND2_X4 1 = "A2"
    inPinName BUF_X1 0 = "A"
    inPinName BUF_X16 0 = "A"
    inPinName BUF_X2 0 = "A"
    inPinName BUF_X32 0 = "A"
    inPinName BUF_X4 0 = "A"
    inPinName BUF_X8 0 = "A"
    inPinName FA_X1 0 = "CI"
    inPinName FA_X1 1 = "A"
    inPinName FA_X1 2 = "B"
    inPinName HA_X1 0 = "A"
    inPinName HA_X1 1 = "B"
    inPinName INV_X1 0 = "A"
    inPinName INV_X16 0 = "A"
    inPinName INV_X2 0 = "A"
    inPinName INV_X32 0 = "A"
    inPinName INV_X4 0 = "A"
    inPinName INV_X8 0 = "A"
    inPinName NAND2_X1 0 = "A1"
    inPinName NAND2_X1 1 = "A2"
    inPinName NAND2_X2 0 = "A1"
    inPinName NAND2_X2 1 = "A2"
    inPinName NAND2_X4 0 = "A1"
    inPinName NAND2_X4 1 = "A2"
    inPinName NOR2_X1 0 = "A1"
    inPinName NOR2_X1 1 = "A2"
    inPinName NOR2_X2 0 = "A1"
    inPinName NOR2_X2 1 = "A2"
    inPinName NOR2_X4 0 = "A1"
    inPinName NOR2_X4 1 = "A2"
    inPinName OR2_X1 0 = "A1"
    inPinName OR2_X1 1 = "A2"
    inPinName OR2_X2 0 = "A1"
    inPinName OR2_X2 1 = "A2"
    inPinName OR2_X4 0 = "A1"
    inPinName OR2_X4 1 = "A2"
    inPinName XNOR2_X1 0 = "A"
    inPinName XNOR2_X1 1 = "B"
    inPinName XNOR2_X2 0 = "A"
    inPinName XNOR2_X2 1 = "B"
    inPinName XOR2_X1 0 = "A"
    inPinName XOR2_X1 1 = "B"
    inPinName XOR2_X2 0 = "A"
    inPinName XOR2_X2 1 = "B"

    outPinName AND2_X1 0 = "ZN"
    outPinName AND2_X2 0 = "ZN"
    outPinName AND2_X4 0 = "ZN"
    outPinName BUF_X1 0 = "Z"
    outPinName BUF_X16 0 = "Z"
    outPinName BUF_X2 0 = "Z"
    outPinName BUF_X32 0 = "Z"
    outPinName BUF_X4 0 = "Z"
    outPinName BUF_X8 0 = "Z"
    outPinName FA_X1 0 = "S"
    outPinName FA_X1 1 = "CO"
    outPinName HA_X1 0 = "S"
    outPinName HA_X1 1 = "CO"
    outPinName INV_X1 0 = "ZN"
    outPinName INV_X16 0 = "ZN"
    outPinName INV_X2 0 = "ZN"
    outPinName INV_X32 0 = "ZN"
    outPinName INV_X4 0 = "ZN"
    outPinName INV_X8 0 = "ZN"
    outPinName LOGIC0_X1 0 = "Z"
    outPinName LOGIC1_X1 0 = "Z"
    outPinName NAND2_X1 0 = "ZN"
    outPinName NAND2_X2 0 = "ZN"
    outPinName NAND2_X4 0 = "ZN"
    outPinName NOR2_X1 0 = "ZN"
    outPinName NOR2_X2 0 = "ZN"
    outPinName NOR2_X4 0 = "ZN"
    outPinName OR2_X1 0 = "ZN"
    outPinName OR2_X2 0 = "ZN"
    outPinName OR2_X4 0 = "ZN"
    outPinName XNOR2_X1 0 = "ZN"
    outPinName XNOR2_X2 0 = "ZN"
    outPinName XOR2_X1 0 = "Z"
    outPinName XOR2_X2 0 = "Z"

    inPinId AND2_X1 "A1" = 0
    inPinId AND2_X1 "A2" = 1
    inPinId AND2_X2 "A1" = 0
    inPinId AND2_X2 "A2" = 1
    inPinId AND2_X4 "A1" = 0
    inPinId AND2_X4 "A2" = 1
    inPinId BUF_X1 "A" = 0
    inPinId BUF_X16 "A" = 0
    inPinId BUF_X2 "A" = 0
    inPinId BUF_X32 "A" = 0
    inPinId BUF_X4 "A" = 0
    inPinId BUF_X8 "A" = 0
    inPinId FA_X1 "CI" = 0
    inPinId FA_X1 "A" = 1
    inPinId FA_X1 "B" = 2
    inPinId HA_X1 "A" = 0
    inPinId HA_X1 "B" = 1
    inPinId INV_X1 "A" = 0
    inPinId INV_X16 "A" = 0
    inPinId INV_X2 "A" = 0
    inPinId INV_X32 "A" = 0
    inPinId INV_X4 "A" = 0
    inPinId INV_X8 "A" = 0
    inPinId NAND2_X1 "A1" = 0
    inPinId NAND2_X1 "A2" = 1
    inPinId NAND2_X2 "A1" = 0
    inPinId NAND2_X2 "A2" = 1
    inPinId NAND2_X4 "A1" = 0
    inPinId NAND2_X4 "A2" = 1
    inPinId NOR2_X1 "A1" = 0
    inPinId NOR2_X1 "A2" = 1
    inPinId NOR2_X2 "A1" = 0
    inPinId NOR2_X2 "A2" = 1
    inPinId NOR2_X4 "A1" = 0
    inPinId NOR2_X4 "A2" = 1
    inPinId OR2_X1 "A1" = 0
    inPinId OR2_X1 "A2" = 1
    inPinId OR2_X2 "A1" = 0
    inPinId OR2_X2 "A2" = 1
    inPinId OR2_X4 "A1" = 0
    inPinId OR2_X4 "A2" = 1
    inPinId XNOR2_X1 "A" = 0
    inPinId XNOR2_X1 "B" = 1
    inPinId XNOR2_X2 "A" = 0
    inPinId XNOR2_X2 "B" = 1
    inPinId XOR2_X1 "A" = 0
    inPinId XOR2_X1 "B" = 1
    inPinId XOR2_X2 "A" = 0
    inPinId XOR2_X2 "B" = 1

    outPinId AND2_X1 "ZN" = 0
    outPinId AND2_X2 "ZN" = 0
    outPinId AND2_X4 "ZN" = 0
    outPinId BUF_X1 "Z" = 0
    outPinId BUF_X16 "Z" = 0
    outPinId BUF_X2 "Z" = 0
    outPinId BUF_X32 "Z" = 0
    outPinId BUF_X4 "Z" = 0
    outPinId BUF_X8 "Z" = 0
    outPinId FA_X1 "S" = 0
    outPinId FA_X1 "CO" = 1
    outPinId HA_X1 "S" = 0
    outPinId HA_X1 "CO" = 1
    outPinId INV_X1 "ZN" = 0
    outPinId INV_X16 "ZN" = 0
    outPinId INV_X2 "ZN" = 0
    outPinId INV_X32 "ZN" = 0
    outPinId INV_X4 "ZN" = 0
    outPinId INV_X8 "ZN" = 0
    outPinId LOGIC0_X1 "Z" = 0
    outPinId LOGIC1_X1 "Z" = 0
    outPinId NAND2_X1 "ZN" = 0
    outPinId NAND2_X2 "ZN" = 0
    outPinId NAND2_X4 "ZN" = 0
    outPinId NOR2_X1 "ZN" = 0
    outPinId NOR2_X2 "ZN" = 0
    outPinId NOR2_X4 "ZN" = 0
    outPinId OR2_X1 "ZN" = 0
    outPinId OR2_X2 "ZN" = 0
    outPinId OR2_X4 "ZN" = 0
    outPinId XNOR2_X1 "ZN" = 0
    outPinId XNOR2_X2 "ZN" = 0
    outPinId XOR2_X1 "Z" = 0
    outPinId XOR2_X2 "Z" = 0

    isFlop AND2_X1 = False
    isFlop AND2_X2 = False
    isFlop AND2_X4 = False
    isFlop BUF_X1 = False
    isFlop BUF_X16 = False
    isFlop BUF_X2 = False
    isFlop BUF_X32 = False
    isFlop BUF_X4 = False
    isFlop BUF_X8 = False
    isFlop FA_X1 = False
    isFlop FILLCELL_X1 = False
    isFlop FILLCELL_X16 = False
    isFlop FILLCELL_X2 = False
    isFlop FILLCELL_X32 = False
    isFlop FILLCELL_X4 = False
    isFlop FILLCELL_X8 = False
    isFlop HA_X1 = False
    isFlop INV_X1 = False
    isFlop INV_X16 = False
    isFlop INV_X2 = False
    isFlop INV_X32 = False
    isFlop INV_X4 = False
    isFlop INV_X8 = False
    isFlop LOGIC0_X1 = False
    isFlop LOGIC1_X1 = False
    isFlop NAND2_X1 = False
    isFlop NAND2_X2 = False
    isFlop NAND2_X4 = False
    isFlop NOR2_X1 = False
    isFlop NOR2_X2 = False
    isFlop NOR2_X4 = False
    isFlop OR2_X1 = False
    isFlop OR2_X2 = False
    isFlop OR2_X4 = False
    isFlop XNOR2_X1 = False
    isFlop XNOR2_X2 = False
    isFlop XOR2_X1 = False
    isFlop XOR2_X2 = False

    lava2000Interp = Interp                      
        { defaultVal = error "Undefined signal"
        , propagator = prop                      
        }                                        
      where                                      
        prop AND2_X1 = \[_, iA1, iA2] -> [Just (L.andl [iA1, iA2]), Nothing, Nothing]
        prop AND2_X2 = \[_, iA1, iA2] -> [Just (L.andl [iA1, iA2]), Nothing, Nothing]
        prop AND2_X4 = \[_, iA1, iA2] -> [Just (L.andl [iA1, iA2]), Nothing, Nothing]
        prop BUF_X1 = \[_, iA] -> [Just (iA), Nothing]
        prop BUF_X16 = \[_, iA] -> [Just (iA), Nothing]
        prop BUF_X2 = \[_, iA] -> [Just (iA), Nothing]
        prop BUF_X32 = \[_, iA] -> [Just (iA), Nothing]
        prop BUF_X4 = \[_, iA] -> [Just (iA), Nothing]
        prop BUF_X8 = \[_, iA] -> [Just (iA), Nothing]
        prop FA_X1 = \[_, _, iCI, iA, iB] -> [Just (L.orl [L.andl [L.orl [L.andl [iA, L.inv (iB)], L.andl [L.inv (iA), iB]], L.inv (iCI)], L.andl [L.inv (L.orl [L.andl [iA, L.inv (iB)], L.andl [L.inv (iA), iB]]), iCI]]), Just (L.orl [L.andl [iA, iB], L.andl [iA, iCI], L.andl [iB, iCI]]), Nothing, Nothing, Nothing]
        prop FILLCELL_X1 = \[] -> []
        prop FILLCELL_X16 = \[] -> []
        prop FILLCELL_X2 = \[] -> []
        prop FILLCELL_X32 = \[] -> []
        prop FILLCELL_X4 = \[] -> []
        prop FILLCELL_X8 = \[] -> []
        prop HA_X1 = \[_, _, iA, iB] -> [Just (L.orl [L.andl [iA, L.inv (iB)], L.andl [L.inv (iA), iB]]), Just (L.andl [iA, iB]), Nothing, Nothing]
        prop INV_X1 = \[_, iA] -> [Just (L.inv (iA)), Nothing]
        prop INV_X16 = \[_, iA] -> [Just (L.inv (iA)), Nothing]
        prop INV_X2 = \[_, iA] -> [Just (L.inv (iA)), Nothing]
        prop INV_X32 = \[_, iA] -> [Just (L.inv (iA)), Nothing]
        prop INV_X4 = \[_, iA] -> [Just (L.inv (iA)), Nothing]
        prop INV_X8 = \[_, iA] -> [Just (L.inv (iA)), Nothing]
        prop LOGIC0_X1 = \[_] -> [Just (L.low)]
        prop LOGIC1_X1 = \[_] -> [Just (L.high)]
        prop NAND2_X1 = \[_, iA1, iA2] -> [Just (L.inv (L.andl [iA1, iA2])), Nothing, Nothing]
        prop NAND2_X2 = \[_, iA1, iA2] -> [Just (L.inv (L.andl [iA1, iA2])), Nothing, Nothing]
        prop NAND2_X4 = \[_, iA1, iA2] -> [Just (L.inv (L.andl [iA1, iA2])), Nothing, Nothing]
        prop NOR2_X1 = \[_, iA1, iA2] -> [Just (L.inv (L.orl [iA1, iA2])), Nothing, Nothing]
        prop NOR2_X2 = \[_, iA1, iA2] -> [Just (L.inv (L.orl [iA1, iA2])), Nothing, Nothing]
        prop NOR2_X4 = \[_, iA1, iA2] -> [Just (L.inv (L.orl [iA1, iA2])), Nothing, Nothing]
        prop OR2_X1 = \[_, iA1, iA2] -> [Just (L.orl [iA1, iA2]), Nothing, Nothing]
        prop OR2_X2 = \[_, iA1, iA2] -> [Just (L.orl [iA1, iA2]), Nothing, Nothing]
        prop OR2_X4 = \[_, iA1, iA2] -> [Just (L.orl [iA1, iA2]), Nothing, Nothing]
        prop XNOR2_X1 = \[_, iA, iB] -> [Just (L.inv (L.orl [L.andl [iA, L.inv (iB)], L.andl [L.inv (iA), iB]])), Nothing, Nothing]
        prop XNOR2_X2 = \[_, iA, iB] -> [Just (L.inv (L.orl [L.andl [iA, L.inv (iB)], L.andl [L.inv (iA), iB]])), Nothing, Nothing]
        prop XOR2_X1 = \[_, iA, iB] -> [Just (L.orl [L.andl [iA, L.inv (iB)], L.andl [L.inv (iA), iB]]), Nothing, Nothing]
        prop XOR2_X2 = \[_, iA, iB] -> [Just (L.orl [L.andl [iA, L.inv (iB)], L.andl [L.inv (iA), iB]]), Nothing, Nothing]

instance TimingLibrary Nangate45
  where
    loadCaps AND2_X1 = [5.05e-16, 5.25e-16]
    loadCaps AND2_X2 = [5.1e-16, 5.41e-16]
    loadCaps AND2_X4 = [4.85e-16, 5.37e-16]
    loadCaps BUF_X1 = [5.04e-16]
    loadCaps BUF_X16 = [4.3399999999999995e-16]
    loadCaps BUF_X2 = [5.109999999999999e-16]
    loadCaps BUF_X32 = [4.519999999999999e-16]
    loadCaps BUF_X4 = [4.66e-16]
    loadCaps BUF_X8 = [4.650000000000001e-16]
    loadCaps FA_X1 = [2.1610000000000002e-15, 2.8769999999999996e-15, 3.0339999999999996e-15]
    loadCaps FILLCELL_X1 = []
    loadCaps FILLCELL_X16 = []
    loadCaps FILLCELL_X2 = []
    loadCaps FILLCELL_X32 = []
    loadCaps FILLCELL_X4 = []
    loadCaps FILLCELL_X8 = []
    loadCaps HA_X1 = [2.9650000000000003e-15, 1.697e-15]
    loadCaps INV_X1 = [4.37e-16]
    loadCaps INV_X16 = [5.511e-15]
    loadCaps INV_X2 = [7.839999999999999e-16]
    loadCaps INV_X32 = [1.0717000000000001e-14]
    loadCaps INV_X4 = [1.4630000000000001e-15]
    loadCaps INV_X8 = [2.8129999999999998e-15]
    loadCaps LOGIC0_X1 = []
    loadCaps LOGIC1_X1 = []
    loadCaps NAND2_X1 = [4.939999999999999e-16, 4.6e-16]
    loadCaps NAND2_X2 = [8.95e-16, 8.63e-16]
    loadCaps NAND2_X4 = [1.7149999999999999e-15, 2.472e-15]
    loadCaps NOR2_X1 = [4.809999999999999e-16, 4.979999999999999e-16]
    loadCaps NOR2_X2 = [8.97e-16, 9.24e-16]
    loadCaps NOR2_X4 = [1.777e-15, 2.05e-15]
    loadCaps OR2_X1 = [5.57e-16, 5.34e-16]
    loadCaps OR2_X2 = [6.089999999999999e-16, 5.299999999999999e-16]
    loadCaps OR2_X4 = [5.779999999999999e-16, 5.31e-16]
    loadCaps XNOR2_X1 = [1.029e-15, 1.151e-15]
    loadCaps XNOR2_X2 = [1.395e-15, 1.586e-15]
    loadCaps XOR2_X1 = [1.059e-15, 1.118e-15]
    loadCaps XOR2_X2 = [1.4369999999999999e-15, 1.576e-15]

    delay AND2_X1 0 0 Falling = tableDelay table_AND2_X1_A1_ZN_fallingDelay table_AND2_X1_A1_ZN_fallingTransition
    delay AND2_X1 0 0 Rising = tableDelay table_AND2_X1_A1_ZN_risingDelay table_AND2_X1_A1_ZN_risingTransition
    delay AND2_X1 1 0 Falling = tableDelay table_AND2_X1_A2_ZN_fallingDelay table_AND2_X1_A2_ZN_fallingTransition
    delay AND2_X1 1 0 Rising = tableDelay table_AND2_X1_A2_ZN_risingDelay table_AND2_X1_A2_ZN_risingTransition
    delay AND2_X2 0 0 Falling = tableDelay table_AND2_X2_A1_ZN_fallingDelay table_AND2_X2_A1_ZN_fallingTransition
    delay AND2_X2 0 0 Rising = tableDelay table_AND2_X2_A1_ZN_risingDelay table_AND2_X2_A1_ZN_risingTransition
    delay AND2_X2 1 0 Falling = tableDelay table_AND2_X2_A2_ZN_fallingDelay table_AND2_X2_A2_ZN_fallingTransition
    delay AND2_X2 1 0 Rising = tableDelay table_AND2_X2_A2_ZN_risingDelay table_AND2_X2_A2_ZN_risingTransition
    delay AND2_X4 0 0 Falling = tableDelay table_AND2_X4_A1_ZN_fallingDelay table_AND2_X4_A1_ZN_fallingTransition
    delay AND2_X4 0 0 Rising = tableDelay table_AND2_X4_A1_ZN_risingDelay table_AND2_X4_A1_ZN_risingTransition
    delay AND2_X4 1 0 Falling = tableDelay table_AND2_X4_A2_ZN_fallingDelay table_AND2_X4_A2_ZN_fallingTransition
    delay AND2_X4 1 0 Rising = tableDelay table_AND2_X4_A2_ZN_risingDelay table_AND2_X4_A2_ZN_risingTransition
    delay BUF_X1 0 0 Falling = tableDelay table_BUF_X1_A_Z_fallingDelay table_BUF_X1_A_Z_fallingTransition
    delay BUF_X1 0 0 Rising = tableDelay table_BUF_X1_A_Z_risingDelay table_BUF_X1_A_Z_risingTransition
    delay BUF_X16 0 0 Falling = tableDelay table_BUF_X16_A_Z_fallingDelay table_BUF_X16_A_Z_fallingTransition
    delay BUF_X16 0 0 Rising = tableDelay table_BUF_X16_A_Z_risingDelay table_BUF_X16_A_Z_risingTransition
    delay BUF_X2 0 0 Falling = tableDelay table_BUF_X2_A_Z_fallingDelay table_BUF_X2_A_Z_fallingTransition
    delay BUF_X2 0 0 Rising = tableDelay table_BUF_X2_A_Z_risingDelay table_BUF_X2_A_Z_risingTransition
    delay BUF_X32 0 0 Falling = tableDelay table_BUF_X32_A_Z_fallingDelay table_BUF_X32_A_Z_fallingTransition
    delay BUF_X32 0 0 Rising = tableDelay table_BUF_X32_A_Z_risingDelay table_BUF_X32_A_Z_risingTransition
    delay BUF_X4 0 0 Falling = tableDelay table_BUF_X4_A_Z_fallingDelay table_BUF_X4_A_Z_fallingTransition
    delay BUF_X4 0 0 Rising = tableDelay table_BUF_X4_A_Z_risingDelay table_BUF_X4_A_Z_risingTransition
    delay BUF_X8 0 0 Falling = tableDelay table_BUF_X8_A_Z_fallingDelay table_BUF_X8_A_Z_fallingTransition
    delay BUF_X8 0 0 Rising = tableDelay table_BUF_X8_A_Z_risingDelay table_BUF_X8_A_Z_risingTransition
    delay FA_X1 0 0 Falling = tableDelay table_FA_X1_CI_S_fallingDelay table_FA_X1_CI_S_fallingTransition
    delay FA_X1 0 0 Rising = tableDelay table_FA_X1_CI_S_risingDelay table_FA_X1_CI_S_risingTransition
    delay FA_X1 0 1 Falling = tableDelay table_FA_X1_CI_CO_fallingDelay table_FA_X1_CI_CO_fallingTransition
    delay FA_X1 0 1 Rising = tableDelay table_FA_X1_CI_CO_risingDelay table_FA_X1_CI_CO_risingTransition
    delay FA_X1 1 0 Falling = tableDelay table_FA_X1_A_S_fallingDelay table_FA_X1_A_S_fallingTransition
    delay FA_X1 1 0 Rising = tableDelay table_FA_X1_A_S_risingDelay table_FA_X1_A_S_risingTransition
    delay FA_X1 1 1 Falling = tableDelay table_FA_X1_A_CO_fallingDelay table_FA_X1_A_CO_fallingTransition
    delay FA_X1 1 1 Rising = tableDelay table_FA_X1_A_CO_risingDelay table_FA_X1_A_CO_risingTransition
    delay FA_X1 2 0 Falling = tableDelay table_FA_X1_B_S_fallingDelay table_FA_X1_B_S_fallingTransition
    delay FA_X1 2 0 Rising = tableDelay table_FA_X1_B_S_risingDelay table_FA_X1_B_S_risingTransition
    delay FA_X1 2 1 Falling = tableDelay table_FA_X1_B_CO_fallingDelay table_FA_X1_B_CO_fallingTransition
    delay FA_X1 2 1 Rising = tableDelay table_FA_X1_B_CO_risingDelay table_FA_X1_B_CO_risingTransition
    delay HA_X1 0 0 Falling = tableDelay table_HA_X1_A_S_fallingDelay table_HA_X1_A_S_fallingTransition
    delay HA_X1 0 0 Rising = tableDelay table_HA_X1_A_S_risingDelay table_HA_X1_A_S_risingTransition
    delay HA_X1 0 1 Falling = tableDelay table_HA_X1_A_CO_fallingDelay table_HA_X1_A_CO_fallingTransition
    delay HA_X1 0 1 Rising = tableDelay table_HA_X1_A_CO_risingDelay table_HA_X1_A_CO_risingTransition
    delay HA_X1 1 0 Falling = tableDelay table_HA_X1_B_S_fallingDelay table_HA_X1_B_S_fallingTransition
    delay HA_X1 1 0 Rising = tableDelay table_HA_X1_B_S_risingDelay table_HA_X1_B_S_risingTransition
    delay HA_X1 1 1 Falling = tableDelay table_HA_X1_B_CO_fallingDelay table_HA_X1_B_CO_fallingTransition
    delay HA_X1 1 1 Rising = tableDelay table_HA_X1_B_CO_risingDelay table_HA_X1_B_CO_risingTransition
    delay INV_X1 0 0 Falling = tableDelay table_INV_X1_A_ZN_fallingDelay table_INV_X1_A_ZN_fallingTransition
    delay INV_X1 0 0 Rising = tableDelay table_INV_X1_A_ZN_risingDelay table_INV_X1_A_ZN_risingTransition
    delay INV_X16 0 0 Falling = tableDelay table_INV_X16_A_ZN_fallingDelay table_INV_X16_A_ZN_fallingTransition
    delay INV_X16 0 0 Rising = tableDelay table_INV_X16_A_ZN_risingDelay table_INV_X16_A_ZN_risingTransition
    delay INV_X2 0 0 Falling = tableDelay table_INV_X2_A_ZN_fallingDelay table_INV_X2_A_ZN_fallingTransition
    delay INV_X2 0 0 Rising = tableDelay table_INV_X2_A_ZN_risingDelay table_INV_X2_A_ZN_risingTransition
    delay INV_X32 0 0 Falling = tableDelay table_INV_X32_A_ZN_fallingDelay table_INV_X32_A_ZN_fallingTransition
    delay INV_X32 0 0 Rising = tableDelay table_INV_X32_A_ZN_risingDelay table_INV_X32_A_ZN_risingTransition
    delay INV_X4 0 0 Falling = tableDelay table_INV_X4_A_ZN_fallingDelay table_INV_X4_A_ZN_fallingTransition
    delay INV_X4 0 0 Rising = tableDelay table_INV_X4_A_ZN_risingDelay table_INV_X4_A_ZN_risingTransition
    delay INV_X8 0 0 Falling = tableDelay table_INV_X8_A_ZN_fallingDelay table_INV_X8_A_ZN_fallingTransition
    delay INV_X8 0 0 Rising = tableDelay table_INV_X8_A_ZN_risingDelay table_INV_X8_A_ZN_risingTransition
    delay NAND2_X1 0 0 Falling = tableDelay table_NAND2_X1_A1_ZN_fallingDelay table_NAND2_X1_A1_ZN_fallingTransition
    delay NAND2_X1 0 0 Rising = tableDelay table_NAND2_X1_A1_ZN_risingDelay table_NAND2_X1_A1_ZN_risingTransition
    delay NAND2_X1 1 0 Falling = tableDelay table_NAND2_X1_A2_ZN_fallingDelay table_NAND2_X1_A2_ZN_fallingTransition
    delay NAND2_X1 1 0 Rising = tableDelay table_NAND2_X1_A2_ZN_risingDelay table_NAND2_X1_A2_ZN_risingTransition
    delay NAND2_X2 0 0 Falling = tableDelay table_NAND2_X2_A1_ZN_fallingDelay table_NAND2_X2_A1_ZN_fallingTransition
    delay NAND2_X2 0 0 Rising = tableDelay table_NAND2_X2_A1_ZN_risingDelay table_NAND2_X2_A1_ZN_risingTransition
    delay NAND2_X2 1 0 Falling = tableDelay table_NAND2_X2_A2_ZN_fallingDelay table_NAND2_X2_A2_ZN_fallingTransition
    delay NAND2_X2 1 0 Rising = tableDelay table_NAND2_X2_A2_ZN_risingDelay table_NAND2_X2_A2_ZN_risingTransition
    delay NAND2_X4 0 0 Falling = tableDelay table_NAND2_X4_A1_ZN_fallingDelay table_NAND2_X4_A1_ZN_fallingTransition
    delay NAND2_X4 0 0 Rising = tableDelay table_NAND2_X4_A1_ZN_risingDelay table_NAND2_X4_A1_ZN_risingTransition
    delay NAND2_X4 1 0 Falling = tableDelay table_NAND2_X4_A2_ZN_fallingDelay table_NAND2_X4_A2_ZN_fallingTransition
    delay NAND2_X4 1 0 Rising = tableDelay table_NAND2_X4_A2_ZN_risingDelay table_NAND2_X4_A2_ZN_risingTransition
    delay NOR2_X1 0 0 Falling = tableDelay table_NOR2_X1_A1_ZN_fallingDelay table_NOR2_X1_A1_ZN_fallingTransition
    delay NOR2_X1 0 0 Rising = tableDelay table_NOR2_X1_A1_ZN_risingDelay table_NOR2_X1_A1_ZN_risingTransition
    delay NOR2_X1 1 0 Falling = tableDelay table_NOR2_X1_A2_ZN_fallingDelay table_NOR2_X1_A2_ZN_fallingTransition
    delay NOR2_X1 1 0 Rising = tableDelay table_NOR2_X1_A2_ZN_risingDelay table_NOR2_X1_A2_ZN_risingTransition
    delay NOR2_X2 0 0 Falling = tableDelay table_NOR2_X2_A1_ZN_fallingDelay table_NOR2_X2_A1_ZN_fallingTransition
    delay NOR2_X2 0 0 Rising = tableDelay table_NOR2_X2_A1_ZN_risingDelay table_NOR2_X2_A1_ZN_risingTransition
    delay NOR2_X2 1 0 Falling = tableDelay table_NOR2_X2_A2_ZN_fallingDelay table_NOR2_X2_A2_ZN_fallingTransition
    delay NOR2_X2 1 0 Rising = tableDelay table_NOR2_X2_A2_ZN_risingDelay table_NOR2_X2_A2_ZN_risingTransition
    delay NOR2_X4 0 0 Falling = tableDelay table_NOR2_X4_A1_ZN_fallingDelay table_NOR2_X4_A1_ZN_fallingTransition
    delay NOR2_X4 0 0 Rising = tableDelay table_NOR2_X4_A1_ZN_risingDelay table_NOR2_X4_A1_ZN_risingTransition
    delay NOR2_X4 1 0 Falling = tableDelay table_NOR2_X4_A2_ZN_fallingDelay table_NOR2_X4_A2_ZN_fallingTransition
    delay NOR2_X4 1 0 Rising = tableDelay table_NOR2_X4_A2_ZN_risingDelay table_NOR2_X4_A2_ZN_risingTransition
    delay OR2_X1 0 0 Falling = tableDelay table_OR2_X1_A1_ZN_fallingDelay table_OR2_X1_A1_ZN_fallingTransition
    delay OR2_X1 0 0 Rising = tableDelay table_OR2_X1_A1_ZN_risingDelay table_OR2_X1_A1_ZN_risingTransition
    delay OR2_X1 1 0 Falling = tableDelay table_OR2_X1_A2_ZN_fallingDelay table_OR2_X1_A2_ZN_fallingTransition
    delay OR2_X1 1 0 Rising = tableDelay table_OR2_X1_A2_ZN_risingDelay table_OR2_X1_A2_ZN_risingTransition
    delay OR2_X2 0 0 Falling = tableDelay table_OR2_X2_A1_ZN_fallingDelay table_OR2_X2_A1_ZN_fallingTransition
    delay OR2_X2 0 0 Rising = tableDelay table_OR2_X2_A1_ZN_risingDelay table_OR2_X2_A1_ZN_risingTransition
    delay OR2_X2 1 0 Falling = tableDelay table_OR2_X2_A2_ZN_fallingDelay table_OR2_X2_A2_ZN_fallingTransition
    delay OR2_X2 1 0 Rising = tableDelay table_OR2_X2_A2_ZN_risingDelay table_OR2_X2_A2_ZN_risingTransition
    delay OR2_X4 0 0 Falling = tableDelay table_OR2_X4_A1_ZN_fallingDelay table_OR2_X4_A1_ZN_fallingTransition
    delay OR2_X4 0 0 Rising = tableDelay table_OR2_X4_A1_ZN_risingDelay table_OR2_X4_A1_ZN_risingTransition
    delay OR2_X4 1 0 Falling = tableDelay table_OR2_X4_A2_ZN_fallingDelay table_OR2_X4_A2_ZN_fallingTransition
    delay OR2_X4 1 0 Rising = tableDelay table_OR2_X4_A2_ZN_risingDelay table_OR2_X4_A2_ZN_risingTransition
    delay XNOR2_X1 0 0 Falling = tableDelay table_XNOR2_X1_A_ZN_fallingDelay table_XNOR2_X1_A_ZN_fallingTransition
    delay XNOR2_X1 0 0 Rising = tableDelay table_XNOR2_X1_A_ZN_risingDelay table_XNOR2_X1_A_ZN_risingTransition
    delay XNOR2_X1 1 0 Falling = tableDelay table_XNOR2_X1_B_ZN_fallingDelay table_XNOR2_X1_B_ZN_fallingTransition
    delay XNOR2_X1 1 0 Rising = tableDelay table_XNOR2_X1_B_ZN_risingDelay table_XNOR2_X1_B_ZN_risingTransition
    delay XNOR2_X2 0 0 Falling = tableDelay table_XNOR2_X2_A_ZN_fallingDelay table_XNOR2_X2_A_ZN_fallingTransition
    delay XNOR2_X2 0 0 Rising = tableDelay table_XNOR2_X2_A_ZN_risingDelay table_XNOR2_X2_A_ZN_risingTransition
    delay XNOR2_X2 1 0 Falling = tableDelay table_XNOR2_X2_B_ZN_fallingDelay table_XNOR2_X2_B_ZN_fallingTransition
    delay XNOR2_X2 1 0 Rising = tableDelay table_XNOR2_X2_B_ZN_risingDelay table_XNOR2_X2_B_ZN_risingTransition
    delay XOR2_X1 0 0 Falling = tableDelay table_XOR2_X1_A_Z_fallingDelay table_XOR2_X1_A_Z_fallingTransition
    delay XOR2_X1 0 0 Rising = tableDelay table_XOR2_X1_A_Z_risingDelay table_XOR2_X1_A_Z_risingTransition
    delay XOR2_X1 1 0 Falling = tableDelay table_XOR2_X1_B_Z_fallingDelay table_XOR2_X1_B_Z_fallingTransition
    delay XOR2_X1 1 0 Rising = tableDelay table_XOR2_X1_B_Z_risingDelay table_XOR2_X1_B_Z_risingTransition
    delay XOR2_X2 0 0 Falling = tableDelay table_XOR2_X2_A_Z_fallingDelay table_XOR2_X2_A_Z_fallingTransition
    delay XOR2_X2 0 0 Rising = tableDelay table_XOR2_X2_A_Z_risingDelay table_XOR2_X2_A_Z_risingTransition
    delay XOR2_X2 1 0 Falling = tableDelay table_XOR2_X2_B_Z_fallingDelay table_XOR2_X2_B_Z_fallingTransition
    delay XOR2_X2 1 0 Rising = tableDelay table_XOR2_X2_B_Z_risingDelay table_XOR2_X2_B_Z_risingTransition

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = and [A1, A2]
and2_x1 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
and2_x1 = cell AND2_X1

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = and [A1, A2]
and2_x2 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
and2_x2 = cell AND2_X2

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = and [A1, A2]
and2_x4 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
and2_x4 = cell AND2_X4

-- | Interface:
--
-- >    A -> Z
--
-- Function:
--
-- >    Z = A
buf_x1 :: MonadLava Nangate45 m => Signal -> m Signal
buf_x1 = cell BUF_X1

-- | Interface:
--
-- >    A -> Z
--
-- Function:
--
-- >    Z = A
buf_x16 :: MonadLava Nangate45 m => Signal -> m Signal
buf_x16 = cell BUF_X16

-- | Interface:
--
-- >    A -> Z
--
-- Function:
--
-- >    Z = A
buf_x2 :: MonadLava Nangate45 m => Signal -> m Signal
buf_x2 = cell BUF_X2

-- | Interface:
--
-- >    A -> Z
--
-- Function:
--
-- >    Z = A
buf_x32 :: MonadLava Nangate45 m => Signal -> m Signal
buf_x32 = cell BUF_X32

-- | Interface:
--
-- >    A -> Z
--
-- Function:
--
-- >    Z = A
buf_x4 :: MonadLava Nangate45 m => Signal -> m Signal
buf_x4 = cell BUF_X4

-- | Interface:
--
-- >    A -> Z
--
-- Function:
--
-- >    Z = A
buf_x8 :: MonadLava Nangate45 m => Signal -> m Signal
buf_x8 = cell BUF_X8

-- | Interface:
--
-- >    (CI, (A, B)) -> (S, CO)
--
-- Function:
--
-- >    S = or [and [or [and [A, B'], and [A', B]], CI'], and [(or [and [A, B'], and [A', B]])', CI]]
-- >    CO = or [and [A, B], and [A, CI], and [B, CI]]
fa_x1 :: MonadLava Nangate45 m => (Signal, (Signal, Signal)) -> m (Signal, Signal)
fa_x1 = cell FA_X1

fillcell_x1 :: MonadLava Nangate45 m => a -> m a
fillcell_x1 = physCell FILLCELL_X1

fillcell_x16 :: MonadLava Nangate45 m => a -> m a
fillcell_x16 = physCell FILLCELL_X16

fillcell_x2 :: MonadLava Nangate45 m => a -> m a
fillcell_x2 = physCell FILLCELL_X2

fillcell_x32 :: MonadLava Nangate45 m => a -> m a
fillcell_x32 = physCell FILLCELL_X32

fillcell_x4 :: MonadLava Nangate45 m => a -> m a
fillcell_x4 = physCell FILLCELL_X4

fillcell_x8 :: MonadLava Nangate45 m => a -> m a
fillcell_x8 = physCell FILLCELL_X8

-- | Interface:
--
-- >    (A, B) -> (S, CO)
--
-- Function:
--
-- >    S = or [and [A, B'], and [A', B]]
-- >    CO = and [A, B]
ha_x1 :: MonadLava Nangate45 m => (Signal, Signal) -> m (Signal, Signal)
ha_x1 = cell HA_X1

-- | Interface:
--
-- >    A -> ZN
--
-- Function:
--
-- >    ZN = A'
inv_x1 :: MonadLava Nangate45 m => Signal -> m Signal
inv_x1 = cell INV_X1

-- | Interface:
--
-- >    A -> ZN
--
-- Function:
--
-- >    ZN = A'
inv_x16 :: MonadLava Nangate45 m => Signal -> m Signal
inv_x16 = cell INV_X16

-- | Interface:
--
-- >    A -> ZN
--
-- Function:
--
-- >    ZN = A'
inv_x2 :: MonadLava Nangate45 m => Signal -> m Signal
inv_x2 = cell INV_X2

-- | Interface:
--
-- >    A -> ZN
--
-- Function:
--
-- >    ZN = A'
inv_x32 :: MonadLava Nangate45 m => Signal -> m Signal
inv_x32 = cell INV_X32

-- | Interface:
--
-- >    A -> ZN
--
-- Function:
--
-- >    ZN = A'
inv_x4 :: MonadLava Nangate45 m => Signal -> m Signal
inv_x4 = cell INV_X4

-- | Interface:
--
-- >    A -> ZN
--
-- Function:
--
-- >    ZN = A'
inv_x8 :: MonadLava Nangate45 m => Signal -> m Signal
inv_x8 = cell INV_X8

-- | Interface:
--
-- >    Z
--
-- Function:
--
-- >    Z = 0
logic0_x1 :: MonadLava Nangate45 m => m Signal
logic0_x1 = sourceCell LOGIC0_X1

-- | Interface:
--
-- >    Z
--
-- Function:
--
-- >    Z = 1
logic1_x1 :: MonadLava Nangate45 m => m Signal
logic1_x1 = sourceCell LOGIC1_X1

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = (and [A1, A2])'
nand2_x1 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
nand2_x1 = cell NAND2_X1

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = (and [A1, A2])'
nand2_x2 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
nand2_x2 = cell NAND2_X2

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = (and [A1, A2])'
nand2_x4 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
nand2_x4 = cell NAND2_X4

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = (or [A1, A2])'
nor2_x1 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
nor2_x1 = cell NOR2_X1

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = (or [A1, A2])'
nor2_x2 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
nor2_x2 = cell NOR2_X2

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = (or [A1, A2])'
nor2_x4 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
nor2_x4 = cell NOR2_X4

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = or [A1, A2]
or2_x1 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
or2_x1 = cell OR2_X1

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = or [A1, A2]
or2_x2 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
or2_x2 = cell OR2_X2

-- | Interface:
--
-- >    (A1, A2) -> ZN
--
-- Function:
--
-- >    ZN = or [A1, A2]
or2_x4 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
or2_x4 = cell OR2_X4

-- | Interface:
--
-- >    (A, B) -> ZN
--
-- Function:
--
-- >    ZN = (or [and [A, B'], and [A', B]])'
xnor2_x1 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
xnor2_x1 = cell XNOR2_X1

-- | Interface:
--
-- >    (A, B) -> ZN
--
-- Function:
--
-- >    ZN = (or [and [A, B'], and [A', B]])'
xnor2_x2 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
xnor2_x2 = cell XNOR2_X2

-- | Interface:
--
-- >    (A, B) -> Z
--
-- Function:
--
-- >    Z = or [and [A, B'], and [A', B]]
xor2_x1 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
xor2_x1 = cell XOR2_X1

-- | Interface:
--
-- >    (A, B) -> Z
--
-- Function:
--
-- >    Z = or [and [A, B'], and [A', B]]
xor2_x2 :: MonadLava Nangate45 m => (Signal, Signal) -> m Signal
xor2_x2 = cell XOR2_X2