clash-lib- CAES Language for Synchronous Hardware - As a Library

Safe HaskellNone



Module that connects all the parts of the CLaSH compiler library



generateVHDL Source


:: BindingMap

Set of functions

-> PrimMap

Primitive / BlackBox Definitions

-> HashMap TyConName TyCon

TyCon cache

-> (HashMap TyConName TyCon -> Type -> Maybe (Either String HWType))

Hardcoded Type -> HWType translator

-> (HashMap TyConName TyCon -> Term -> Term)

Hardcoded evaluator (delta-reduction)

-> DebugLevel

Debug information level for the normalization process

-> IO () 

Create a set of .VHDL files for a set of functions

createVHDL :: VHDLState -> [Component] -> [(String, Doc)] Source

Pretty print Components to VHDL Documents

prepareDir :: String -> IO () Source

Prepares the directory for writing VHDL files. This means creating the dir if it does not exist and removing all existing .vhdl files from it.

writeVHDL :: FilePath -> (String, Doc) -> IO () Source

Writes a VHDL file to the given directory