Changelog for the clash-lib package

0.4 November 17th 2014

• New features:

  • Support for clash-prelude 0.6

• Fixes bugs:

  • Ambiguous type: 'std_logic_vector' or 'std_ulogic_vector' #33

0.3.2 June 5th 2014

• Fixes bugs:
  • VHDL array constant ambiguous #18
  • Exception: can't create selector #24
  • Calls to vhdlTypeMark don't result to inclusion of VHDL type in types.vhdl #28

0.3.1 May 15th 2014

• New features:

  • Make ANF lift non-representable values #7
  • Hardcode fromInteger for Signed and Unsigned #9
  • Replace VHDL default hole by error hole #13

• Fixes bugs:

  • Type families are not expanded #3
  • Exception: CLaSH.Netlist.VHDL(512): fromSLV: Vector 13 Bool #5
  • Incorrect vhdl generation for default value in blackbox #6
  • Duplicate type names when multiple ADTs need the same amount of bits #8
  • Circuit testbench generation with MAC example fails#15

• Code improvements:

  • Refactor Netlist/BlackBox #10
  • CPP special-case conversion of Control.Exception.Base.irrefutPatError #11