clash-prelude: CAES Language for Synchronous Hardware - Prelude library

[ bsd2, hardware, library ] [ Propose Tags ]

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

This package provides:

To use the library:

A preliminary version of a tutorial can be found in CLaSH.Tutorial, for a general overview of the library you should however check out CLaSH.Prelude. Some circuit examples can be found in CLaSH.Examples.


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Change log CHANGELOG.md
Dependencies array (>=0.5.1.0), base (>=4.8.0.0 && <5), data-default (>=0.5.3), ghc-prim (>=0.3.1.0), ghc-typelits-extra (>=0.1), ghc-typelits-natnormalise (>=0.4.1), integer-gmp (>=0.5.1.0), lens (>=4.9), QuickCheck (>=2.7 && <2.9), reflection (>=2), singletons (>=1.0 && <3.0), template-haskell (>=2.9.0.0), th-lift (>=0.5.6) [details]
License BSD-2-Clause
Copyright Copyright © 2013-2016 University of Twente
Author Christiaan Baaij
Maintainer Christiaan Baaij <christiaan.baaij@gmail.com>
Category Hardware
Home page http://www.clash-lang.org/
Bug tracker http://github.com/clash-lang/clash-prelude/issues
Source repo head: git clone https://github.com/clash-lang/clash-prelude.git
Uploaded by ChristiaanBaaij at Tue Jun 7 13:38:25 UTC 2016
Distributions Arch:0.99.3, NixOS:1.0.1
Downloads 22384 total (1201 in the last 30 days)
Rating 2.25 (votes: 2) [estimated by rule of succession]
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CλaSH - A functional hardware description language

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WARNING Only works with GHC-7.10.* (http://www.haskell.org/ghc/download_ghc_7_10_3)!

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum