clash-prelude-0.6: CAES Language for Synchronous Hardware - Prelude library

Safe HaskellNone
LanguageHaskell2010

CLaSH.Prelude.BlockRam

Synopsis

Documentation

blockRam Source

Arguments

:: (KnownNat n, KnownNat m) 
=> Vec n a

Initial content of the BRAM, also determines the size, n, of the BRAM.

NB: MUST be a constant.

-> Signal (Unsigned m)

Write address w

-> Signal (Unsigned m)

Read address r

-> Signal Bool

Write enable

-> Signal a

Value to write (at address w)

-> Signal a

Value of the blockRAM at address r from the previous clock cycle

Create a blockRAM with space for n elements.

  • NB: Read value is delayed by 1 cycle
  • NB: Initial output value is undefined
bram40 :: Signal (Unsigned 6) -> Signal (Unsigned 6) -> Signal Bool
       -> Signal Bit -> Signal Bit
bram40 = blockRam (replicate d40 H)

blockRamPow2 Source

Arguments

:: (KnownNat (2 ^ n), KnownNat n) 
=> Vec (2 ^ n) a

Initial content of the BRAM, also determines the size, 2^n, of the BRAM.

NB: MUST be a constant.

-> Signal (Unsigned n)

Write address w

-> Signal (Unsigned n)

Read address r

-> Signal Bool

Write enable

-> Signal a

Value to write (at address w)

-> Signal a

Value of the blockRAM at address r from the previous clock cycle

Create a blockRAM with space for 2^n elements

  • NB: Read value is delayed by 1 cycle
  • NB: Initial output value is undefined
bram32 :: Signal (Unsigned 5) -> Signal (Unsigned 5) -> Signal Bool
       -> Signal Bit -> Signal Bit
bram32 = blockRamPow2 (replicate d32 H)

cblockRam Source

Arguments

:: (KnownNat n, KnownNat m) 
=> SClock clk

Clock to synchronize to

-> Vec n a

Initial content of the BRAM, also determines the size, n, of the BRAM.

NB: MUST be a constant.

-> CSignal clk (Unsigned m)

Write address w

-> CSignal clk (Unsigned m)

Read address r

-> CSignal clk Bool

Write enable

-> CSignal clk a

Value to write (at address w)

-> CSignal clk a

Value of the blockRAM at address r from the previous clock cycle

Create a blockRAM with space for n elements

  • NB: Read value is delayed by 1 cycle
  • NB: Initial output value is undefined
type ClkA = Clk "A" 100

clkA100 :: SClock ClkA
clkA100 = sclock

bram40 :: CSignal ClkA (Unsigned 6) -> CSignal ClkA (Unsigned 6)
       -> CSignal ClkA Bool -> CSignal ClkA Bit -> ClkA CSignal Bit
bram40 = cblockRam clkA100 (replicate d40 H)

cblockRamPow2 Source

Arguments

:: (KnownNat n, KnownNat (2 ^ n)) 
=> SClock clk

Clock to synchronize to

-> Vec (2 ^ n) a

Initial content of the BRAM, also determines the size, 2^n, of the BRAM.

NB: MUST be a constant.

-> CSignal clk (Unsigned n)

Write address w

-> CSignal clk (Unsigned n)

Read address r

-> CSignal clk Bool

Write enable

-> CSignal clk a

Value to write (at address w)

-> CSignal clk a

Value of the blockRAM at address r from the previous clock cycle

Create a blockRAM with space for 2^n elements

  • NB: Read value is delayed by 1 cycle
  • NB: Initial output value is undefined
type ClkA = Clk "A" 100

clkA100 :: SClock ClkA
clkA100 = sclock

bramC32 :: CSignal ClkA (Unsigned 5) -> CSignal ClkA (Unsigned 5)
        -> CSignal ClkA Bool -> CSignal ClkA Bit -> CSignal ClkA Bit
bramC32 = cblockRamPow2 clkA100 (replicate d32 H)