Safe Haskell | None |
---|---|
Language | Haskell2010 |
- blockRam :: (KnownNat n, KnownNat m) => Vec n a -> Signal (Unsigned m) -> Signal (Unsigned m) -> Signal Bool -> Signal a -> Signal a
- blockRamPow2 :: (KnownNat (2 ^ n), KnownNat n) => Vec (2 ^ n) a -> Signal (Unsigned n) -> Signal (Unsigned n) -> Signal Bool -> Signal a -> Signal a
- cblockRam :: (KnownNat n, KnownNat m) => SClock clk -> Vec n a -> CSignal clk (Unsigned m) -> CSignal clk (Unsigned m) -> CSignal clk Bool -> CSignal clk a -> CSignal clk a
- cblockRamPow2 :: (KnownNat n, KnownNat (2 ^ n)) => SClock clk -> Vec (2 ^ n) a -> CSignal clk (Unsigned n) -> CSignal clk (Unsigned n) -> CSignal clk Bool -> CSignal clk a -> CSignal clk a
Documentation
:: (KnownNat n, KnownNat m) | |
=> Vec n a | Initial content of the BRAM, also
determines the size, NB: MUST be a constant. |
-> Signal (Unsigned m) | Write address |
-> Signal (Unsigned m) | Read address |
-> Signal Bool | Write enable |
-> Signal a | Value to write (at address |
-> Signal a | Value of the |
Create a blockRAM with space for n
elements.
- NB: Read value is delayed by 1 cycle
- NB: Initial output value is
undefined
bram40 :: Signal (Unsigned 6) -> Signal (Unsigned 6) -> Signal Bool -> Signal Bit -> Signal Bit bram40 = blockRam (replicate d40 H)
:: (KnownNat (2 ^ n), KnownNat n) | |
=> Vec (2 ^ n) a | Initial content of the BRAM, also
determines the size, NB: MUST be a constant. |
-> Signal (Unsigned n) | Write address |
-> Signal (Unsigned n) | Read address |
-> Signal Bool | Write enable |
-> Signal a | Value to write (at address |
-> Signal a | Value of the |
Create a blockRAM with space for 2^n
elements
- NB: Read value is delayed by 1 cycle
- NB: Initial output value is
undefined
bram32 :: Signal (Unsigned 5) -> Signal (Unsigned 5) -> Signal Bool -> Signal Bit -> Signal Bit bram32 = blockRamPow2 (replicate d32 H)
:: (KnownNat n, KnownNat m) | |
=> SClock clk |
|
-> Vec n a | Initial content of the BRAM, also
determines the size, NB: MUST be a constant. |
-> CSignal clk (Unsigned m) | Write address |
-> CSignal clk (Unsigned m) | Read address |
-> CSignal clk Bool | Write enable |
-> CSignal clk a | Value to write (at address |
-> CSignal clk a | Value of the |
Create a blockRAM with space for n
elements
- NB: Read value is delayed by 1 cycle
- NB: Initial output value is
undefined
type ClkA = Clk "A" 100 clkA100 :: SClock ClkA clkA100 = sclock bram40 :: CSignal ClkA (Unsigned 6) -> CSignal ClkA (Unsigned 6) -> CSignal ClkA Bool -> CSignal ClkA Bit -> ClkA CSignal Bit bram40 = cblockRam clkA100 (replicate d40 H)
:: (KnownNat n, KnownNat (2 ^ n)) | |
=> SClock clk |
|
-> Vec (2 ^ n) a | Initial content of the BRAM, also
determines the size, NB: MUST be a constant. |
-> CSignal clk (Unsigned n) | Write address |
-> CSignal clk (Unsigned n) | Read address |
-> CSignal clk Bool | Write enable |
-> CSignal clk a | Value to write (at address |
-> CSignal clk a | Value of the |
Create a blockRAM with space for 2^n
elements
- NB: Read value is delayed by 1 cycle
- NB: Initial output value is
undefined
type ClkA = Clk "A" 100 clkA100 :: SClock ClkA clkA100 = sclock bramC32 :: CSignal ClkA (Unsigned 5) -> CSignal ClkA (Unsigned 5) -> CSignal ClkA Bool -> CSignal ClkA Bit -> CSignal ClkA Bit bramC32 = cblockRamPow2 clkA100 (replicate d32 H)