clash-prelude-0.99.3: CAES Language for Synchronous Hardware - Prelude library

Clash.Explicit.Testbench

Contents

Description

Synopsis

# Testbench functions for circuits

Arguments

 :: (Eq a, ShowX a) => Clock domain gated -> Reset domain synchronous -> String Additional message -> Signal domain a Checked value -> Signal domain a Expected value -> Signal domain b Return value -> Signal domain b

Compares the first two Signals for equality and logs a warning when they are not equal. The second Signal is considered the expected value. This function simply returns the third Signal' unaltered as its result. This function is used by outputVerifier.

NB: This function can be used in synthesizable designs.

Arguments

 :: KnownNat l => Clock domain gated Clock to which to synchronize the output signal -> Reset domain synchronous -> Vec l a Samples to generate -> Signal domain a Signal of given samples

To be used as one of the functions to create the "magical" testInput value, which the CλaSH compiler looks for to create the stimulus generator for the generated VHDL testbench.

Example:

testInput
:: Clock domain gated -> Reset domain synchronous
-> Signal domain Int
testInput clk rst = stimuliGenerator clk rst $(listToVecTH [(1::Int),3..21])  >>> sampleN 13 (testInput systemClockGen systemResetGen) [1,3,5,7,9,11,13,15,17,19,21,21,21]  Arguments  :: (KnownNat l, Eq a, ShowX a) => Clock domain gated Clock to which the input signal is synchronized to -> Reset domain synchronous -> Vec l a Samples to compare with -> Signal domain a Signal to verify -> Signal domain Bool Indicator that all samples are verified To be used as one of the functions to generate the "magical" expectedOutput function, which the CλaSH compiler looks for to create the signal verifier for the generated VHDL testbench. Example: expectedOutput :: Clock domain gated -> Reset domain synchronous -> Signal domain Int -> Signal domain Bool expectedOutput clk rst = outputVerifier clk rst$(listToVecTH ([70,99,2,3,4,5,7,8,9,10]::[Int]))

>>> import qualified Data.List as List
>>> sampleN 12 (expectedOutput systemClockGen systemResetGen (fromList ([0..10] List.++ [10,10,10])))

cycle(system10000): 0, outputVerifier
expected value: 70, not equal to actual value: 0
[False
cycle(system10000): 1, outputVerifier
expected value: 99, not equal to actual value: 1
,False,False,False,False,False
cycle(system10000): 6, outputVerifier
expected value: 7, not equal to actual value: 6
,False
cycle(system10000): 7, outputVerifier
expected value: 8, not equal to actual value: 7
,False
cycle(system10000): 8, outputVerifier
expected value: 9, not equal to actual value: 8
,False
cycle(system10000): 9, outputVerifier
expected value: 10, not equal to actual value: 9
,False,True,True]