The clash-verilog package

[Tags:bsd2, library]

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

This package provides:


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Versions 0.5.5, 0.5.6, 0.5.7, 0.5.8, 0.5.9, 0.5.10, 0.6, 0.6.1, 0.6.2, 0.6.3, 0.6.4, 0.6.5, 0.6.6, 0.6.7, 0.6.8, 0.6.9, 0.6.10, 0.7
Change log CHANGELOG.md
Dependencies base (>=4.6.0.1 && <5), clash-lib (==0.7.*), clash-prelude (==0.11.*), fgl (>=5.4.2.4 && <5.6), hashable (>=1.2.1.0 && <1.3), lens (>=3.9.2 && <4.16), mtl (>=2.1.2 && <2.3), text (>=0.11.3.1 && <1.3), unordered-containers (>=0.2.3.3 && <0.3), wl-pprint-text (>=1.1.0.0 && <1.2) [details]
License BSD2
Copyright Copyright © 2015-2016 University of Twente, 2017, QBayLogic
Author Christiaan Baaij
Maintainer Christiaan Baaij <christiaan.baaij@gmail.com>
Stability Unknown
Category Hardware
Home page http://www.clash-lang.org/
Bug tracker http://github.com/clash-lang/clash-compiler/issues
Source repository head: git clone https://github.com/clash-lang/clash-compiler.git
Uploaded Mon Jan 16 22:56:07 UTC 2017 by ChristiaanBaaij
Distributions LTSHaskell:0.7, NixOS:0.7, Stackage:0.7, Tumbleweed:0.7
Downloads 1307 total (42 in the last 30 days)
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Status Docs uploaded by user
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Readme for clash-verilog

Readme for clash-verilog-0.7

clash-verilog - Verilog backend for the CλaSH compiler

  • See the LICENSE file for license and copyright details

CλaSH - A functional hardware description language

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum