Ice40.Pll.Core

PLL Core hard IP primitive from Lattice Ice Technology Library. The PLL core primitive should be used when the source clock of the PLL is driven by FPGA routing i.e. when the PLL source clock originates on the FPGA or is driven by an input pad the is not in the bottom IO bank (IO Bank 2).

Documentation

pllCorePrim

Arguments

:: KnownDomain dom'

=> BitVector 7

divf

-> BitVector 3

divq

-> BitVector 4

divr

-> String

feedbackPath

-> BitVector 3

filterRange

-> String

pllOutSelect

-> String

delayAdjustmentModeFeedback

-> String

delayAdjustmentModeRelative

-> BitVector 4

fdaFeedback

-> BitVector 4

fdaRelative

-> Bit

enableIceGate

-> Clock dom

referenceClk

-> Signal dom (BitVector 8)

dynamicDelay

-> Signal dom Bit

resetb

-> Signal dom Bit

bypass

-> (Clock dom', Clock dom', Signal dom' Bool)

(pllOutCore, globalOutCore, lock)

PLL Core primitive