System.RedPitaya.Bus.RedPitayaSimple

Documentation

type RpBusAddress = Unsigned 32

type FullAddress = Unsigned 20

type FullDataIn = Unsigned 32

type FullDataOut = Unsigned 32

type WriteByteSel = Unsigned 4

data RpBusSysIn

Constructors

RpBusSysIn

Fields

• addrRpBus :: RpBusAddress
• dataInRpBus :: FullDataIn
• strobeWidthRpBus :: WriteByteSel
• writeEnableRpBus :: Bool
• readEnableRpBus :: Bool

Instances

Show RpBusSysIn

Methods

showsPrec :: Int -> RpBusSysIn -> ShowS

show :: RpBusSysIn -> String

showList :: [RpBusSysIn] -> ShowS

data RpBusSysOut

Constructors

RpBusSysOut

Fields

• dataOut :: FullDataOut
• ack :: Bool
• err :: Bool

Instances

Show RpBusSysOut

Methods

showsPrec :: Int -> RpBusSysOut -> ShowS

show :: RpBusSysOut -> String

showList :: [RpBusSysOut] -> ShowS

data ReadWrite

Constructors

Read

Write

type BusIn = Maybe (FullAddress, ReadWrite, FullDataIn)

type BusOut = Maybe FullDataOut

defTopRedPitayaSimple :: TopEntity

this definition should be used to define bus that can be directly build with fpga core defined in redpitaya branch clash https://github.com/ra1u/RedPitaya/tree/clash

rpSimpleBind :: (Signal BusIn -> Signal BusOut) -> Signal RpBusSysIn -> Signal RpBusSysOut

provide redPitayaSimple interface ovet simplified bus where redPitayaSimple is bus as defined https://github.com/ra1u/RedPitaya/blob/clash/fpga/rtl/red_pitaya_top.v

addrLow :: Signal BusIn -> Signal BusIn

remove away MSB part of address with page info away