name:           netlist
version:        0.3.1
synopsis:       Netlist AST
description:    A very simplified and generic netlist designed to be compatible with
                Hardware Description Languages (HDLs) like Verilog and VHDL.
                Includes a simple inliner.
category:       Language
license:        BSD3
license-file:   LICENSE
copyright:      Copyright (c) 2010 Signali Corp.
                Copyright (c) 2010 Philip Weaver.
author:         Philip Weaver <philip.weaver@gmail.com>
maintainer:     andygill@ku.edu
package-url:    git://github.com/pheaver/netlist-verilog.git
build-type:     Simple
cabal-version:  >=1.6

flag base4
   Description: Compile using base-4 instead of base-3
   Default: True

Library
  ghc-options:          -Wall

  exposed-modules:      Language.Netlist.AST,
                        Language.Netlist.Inline,
                        Language.Netlist.Util
  other-modules:        Language.Netlist.Examples

  build-depends:      binary, containers
  if flag(base4)
     build-depends:   base == 4.*, syb
  else
     build-depends:   base == 3.*