Build #6 for verilog-0.0.8
| Package | verilog-0.0.8 |
|---|
| Install | BuildFailed |
|---|---|
| Docs | NotTried |
| Tests | NotTried |
| Time submitted | 2016-12-12 17:04:29.225067 UTC |
|---|---|
| Compiler | ghc-8.0.1.20161018 |
| OS | linux |
| Arch | x86_64 |
| Dependencies | array-0.5.1.1, base-4.9.0.0, monadLib-3.7.3 |
| Flags | none |
Code Coverage
No Code Coverage was submitted for this report.
Build log
[view raw]
Resolving dependencies...
Configuring monadLib-3.7.3...
Building monadLib-3.7.3...
Installed monadLib-3.7.3
Configuring verilog-0.0.8...
Building verilog-0.0.8...
Failed to install verilog-0.0.8
Build log ( /home/builder/.cabal/logs/verilog-0.0.8.log ):
cabal: Entering directory '/tmp/cabal-tmp-17288/verilog-0.0.8'
Configuring verilog-0.0.8...
Building verilog-0.0.8...
Preprocessing library verilog-0.0.8...
[1 of 9] Compiling Language.Verilog.Parser.Tokens ( Language/Verilog/Parser/Tokens.hs, dist/build/Language/Verilog/Parser/Tokens.o )
[2 of 9] Compiling Language.Verilog.Parser.Preprocess ( Language/Verilog/Parser/Preprocess.hs, dist/build/Language/Verilog/Parser/Preprocess.o )
[3 of 9] Compiling Language.Verilog.Parser.Lex ( dist/build/Language/Verilog/Parser/Lex.hs, dist/build/Language/Verilog/Parser/Lex.o )
dist/build/Language/Verilog/Parser/Lex.hs:428:32: error:
• Couldn't match expected type ‘[AlexAcc
(AlexPosn -> String -> Token) t]’
with actual type ‘e0’
because type variable ‘t’ would escape its scope
This (rigid, skolem) type variable is bound by
the inferred type of
alex_scan_tkn :: t
-> AlexInput
-> Int#
-> AlexInput
-> Int#
-> AlexLastAcc (AlexPosn -> String -> Token)
-> (AlexLastAcc (AlexPosn -> String -> Token),
(AlexPosn, Char, [Byte], String))
at dist/build/Language/Verilog/Parser/Lex.hs:(425,1)-(465,47)
• In the first argument of ‘check_accs’, namely
‘(alex_accept `quickIndex` (I# (s)))’
In the expression: (check_accs (alex_accept `quickIndex` (I# (s))))
In an equation for ‘new_acc’:
new_acc = (check_accs (alex_accept `quickIndex` (I# (s))))
• Relevant bindings include
check_accs :: [AlexAcc (AlexPosn -> String -> Token) t]
-> AlexLastAcc (AlexPosn -> String -> Token)
(bound at dist/build/Language/Verilog/Parser/Lex.hs:456:9)
user :: t
(bound at dist/build/Language/Verilog/Parser/Lex.hs:425:15)
alex_scan_tkn :: t
-> AlexInput
-> Int#
-> AlexInput
-> Int#
-> AlexLastAcc (AlexPosn -> String -> Token)
-> (AlexLastAcc (AlexPosn -> String -> Token),
(AlexPosn, Char, [Byte], String))
(bound at dist/build/Language/Verilog/Parser/Lex.hs:425:1)
dist/build/Language/Verilog/Parser/Lex.hs:439:17: error:
• Pattern bindings containing unlifted types should use an outermost bang pattern:
((I# (ord_c))) = fromIntegral c
• In the expression:
let
(base) = alexIndexInt32OffAddr alex_base s
((I# (ord_c))) = fromIntegral c
(offset) = (base +# ord_c)
....
in
case new_s of {
-1# -> (new_acc, input)
_ -> alex_scan_tkn
user
orig_input
(if c < 128 || c >= 192 then (len +# 1#) else len)
new_input
new_s
new_acc }
In a case alternative:
Just (c, new_input)
-> let
(base) = alexIndexInt32OffAddr alex_base s
((I# (ord_c))) = fromIntegral c
....
in
case new_s of {
-1# -> (new_acc, input)
_ -> alex_scan_tkn
user
orig_input
(if c < 128 || c >= 192 then (len +# 1#) else len)
new_input
new_s
new_acc }
In the second argument of ‘seq’, namely
‘case alexGetByte input of {
Nothing -> (new_acc, input)
Just (c, new_input)
-> let
(base) = ...
....
in
case new_s of {
-1# -> ...
_ -> alex_scan_tkn
user
orig_input
(if c < 128 || c >= 192 then (len +# 1#) else len)
new_input
new_s
new_acc } }’
dist/build/Language/Verilog/Parser/Lex.hs:443:31: error:
• Couldn't match expected type ‘Bool’ with actual type ‘Int#’
• In the first argument of ‘(&&)’, namely ‘(offset >=# 0#)’
In the expression: (offset >=# 0#) && (check ==# ord_c)
In the expression:
if (offset >=# 0#) && (check ==# ord_c) then
alexIndexInt16OffAddr alex_table offset
else
alexIndexInt16OffAddr alex_deflt s
dist/build/Language/Verilog/Parser/Lex.hs:443:50: error:
• Couldn't match expected type ‘Bool’ with actual type ‘Int#’
• In the second argument of ‘(&&)’, namely ‘(check ==# ord_c)’
In the expression: (offset >=# 0#) && (check ==# ord_c)
In the expression:
if (offset >=# 0#) && (check ==# ord_c) then
alexIndexInt16OffAddr alex_table offset
else
alexIndexInt16OffAddr alex_deflt s
cabal: Leaving directory '/tmp/cabal-tmp-17288/verilog-0.0.8'
cabal: Error: some packages failed to install:
verilog-0.0.8 failed during the building phase. The exception was:
ExitFailure 1
Test log
No test log was submitted for this report.