Verismith.Verilog.Internal

Defaults and common functions.

Documentation

regDecl :: Identifier -> ModItem

wireDecl :: Identifier -> ModItem

emptyMod :: ModDecl

Create an empty module.

setModName :: Text -> ModDecl -> ModDecl

Set a module name for a module declaration.

addModPort :: Port -> ModDecl -> ModDecl

Add a input port to the module declaration.

addModDecl :: ModDecl -> Verilog -> Verilog

testBench :: ModDecl

addTestBench :: Verilog -> Verilog

defaultPort :: Identifier -> Port

portToExpr :: Port -> Expr

modName :: ModDecl -> Text

yPort :: Identifier -> Port

wire :: Range -> Identifier -> Port

reg :: Range -> Identifier -> Port