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--- $Id: ComputeNetlist.hs#6 2010/09/21 17:21:45 REDMOND\\satnams $
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module Lava.ComputeNetlist (-- * Generating a Lava netlist
                            computeNetlist
                            )
where

import Control.Monad.State

import Lava.ApplyLayout
import Lava.Netlist

-------------------------------------------------------------------------------

computeNetlist :: XilinxArchitecture -> Out () -> Netlist
computeNetlist architecture circuit
  = if nesting /= 0 then
      error ("Final layout nesting is not zero (" ++ show nesting ++ ")")
    else
      applyLayout netlist
    where
    netlist = execState circuit (Netlist [] [] 0 0 [] 0 undefined architecture)
    nesting = layoutNesting netlist
 
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