Xilinx Lava is a library for FPGA circuit design with a focus on circuit layout.
- (>->) :: (a -> Out b) -> (b -> Out c) -> a -> Out c
- (>|>) :: (a -> Out b) -> (b -> Out c) -> a -> Out c
- hRepN :: Int -> (a -> Out a) -> a -> Out a
- par2 :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)
- par2Overlay :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)
- par3Overlay :: (a -> Out ao) -> (b -> Out bo) -> (c -> Out co) -> (a, b, c) -> Out (ao, bo, co)
- hpar :: [a -> Out b] -> [a] -> Out [b]
- hparN :: Int -> (a -> Out b) -> [a] -> Out [b]
- fork2 :: a -> Out (a, a)
- listToPair :: [a] -> Out (a, a)
- pairToList :: (a, a) -> Out [a]
- ziP :: ([a], [b]) -> Out [(a, b)]
- unziP :: [(a, b)] -> Out ([a], [b])
- zipList :: [[a]] -> Out [[a]]
- unzipList :: [[a]] -> Out [[a]]
- fstListPair :: [a] -> a
- sndListPair :: [a] -> a
- pair :: [a] -> Out [[a]]
- unpair :: [[a]] -> Out [a]
- halve :: [a] -> Out ([a], [a])
- unhalve :: ([a], [a]) -> Out [a]
- halveList :: [a] -> Out [[a]]
- unhalveList :: [[a]] -> Out [a]
- chop :: Int -> [a] -> Out [[a]]
- concaT :: [[a]] -> Out [a]
- fstList :: ([a] -> Out [a]) -> [a] -> Out [a]
- sndList :: ([a] -> Out [a]) -> [a] -> Out [a]
- fsT :: (a -> Out b) -> (a, c) -> Out (b, c)
- snD :: (b -> Out c) -> (a, b) -> Out (a, c)
- reversE :: [a] -> Out [a]
- inputPort :: String -> NetType -> Out Bit
- inputBitVec :: String -> NetType -> Out [Bit]
- outputPort :: String -> NetType -> Bit -> Out ()
- outputBitVec :: String -> NetType -> [Bit] -> Out ()
- data Dir
- data NetType
- data Netlist
- type Out a = State Netlist a
- type Bit = Int
- data XilinxArchitecture
- computeNetlist :: XilinxArchitecture -> Out () -> Netlist
- putXilinxVHDL :: String -> Netlist -> IO ()
- overlayTile :: Out a -> Out a
- primitiveGate :: String -> [(String, Bit)] -> [String] -> Maybe (Int, Int) -> Out [Bit]
- lavaVersion :: (Int, Int, Int, Int)
Lava Combinators
Serial composition combinators
(>->) :: (a -> Out b) -> (b -> Out c) -> a -> Out cSource
Serial composition with horizontal left to right layout
Parallel composition combinators
par2 :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)Source
Horizontal parallel composition of two circuits
par2Overlay :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)Source
Parallel composition of two circuit which have overlaid layout
par3Overlay :: (a -> Out ao) -> (b -> Out bo) -> (c -> Out co) -> (a, b, c) -> Out (ao, bo, co)Source
Parallel composition of three circuit which have overlaid layout
hparN :: Int -> (a -> Out b) -> [a] -> Out [b]Source
Horizontal repeated parallel composition of a circuit
Wiring combinators
listToPair :: [a] -> Out (a, a)Source
Converts a two element list into a pair
pairToList :: (a, a) -> Out [a]Source
Converts a par into a list containing two elements
zipList :: [[a]] -> Out [[a]]Source
Takes a list containing two elements and returns a list of lists where each element is a two element list
fstListPair :: [a] -> aSource
sndListPair :: [a] -> aSource
halve :: [a] -> Out ([a], [a])Source
Tales a list and returns a pair containing the two halves of the list
unhalveList :: [[a]] -> Out [a]Source
Undoes halveList
Circuit input/output ports
inputBitVec :: String -> NetType -> Out [Bit]Source
inputBitVec
creates a bit-vector input port
outputPort :: String -> NetType -> Bit -> Out ()Source
outputPort
creates a single bit output port
outputBitVec :: String -> NetType -> [Bit] -> Out ()Source
outputBitVec
creates a bit-vector output port
data XilinxArchitecture Source
Generating a Lava netlist
computeNetlist :: XilinxArchitecture -> Out () -> NetlistSource
overlayTile :: Out a -> Out aSource
overlayTile takes a circuit instantiation block and overlays all the the instantions.
Adding new primitive gates to the Lava system
:: String | The name of the component |
-> [(String, Bit)] | name of input ports with argument nets |
-> [String] | name of output ports |
-> Maybe (Int, Int) | optional size information for layout |
-> Out [Bit] | a list of output nets from this component |
primitiveGate
adds a primitive gate