module Lava.ComputeNetlist (
computeNetlist
)
where
import Control.Monad.State
import Lava.ApplyLayout
import Lava.Netlist
computeNetlist :: XilinxArchitecture -> Out () -> Netlist
computeNetlist architecture circuit
= if nesting /= 0 then
error ("Final layout nesting is not zero (" ++ show nesting ++ ")")
else
if length l > 2 then
error ("Currently Lava only supports one top level layout group.")
else
applyLayout netlist
where
netlist = execState circuit (Netlist [] [] 0 0 [] 0 undefined architecture)
nesting = layoutNesting netlist
l = layout netlist