xilinx-lava-5.0.1.2: The Lava system for Xilinx FPGA design with layout combinators.

Lava.Virtex4

Contents

Description

The Lava.Unisim module defines the basic gates that are common to all architectures.

Synopsis

Lava Gates

LUT-based gates

invSource

Arguments

:: Bit

The input i0

-> Out Bit

The output o

The inv function implements an invertor explicitly with a LUT1.

and2Source

Arguments

:: (Bit, Bit)

inputs (i0, i1)

-> Out Bit

output o

The and2 function implements an AND gate explicitly with a LUT2.

and3Source

Arguments

:: (Bit, Bit, Bit)

inputs (i0, i1, i2)

-> Out Bit

output o

The and3 function implements an AND gate explicitly with a LUT3.

and4Source

Arguments

:: (Bit, Bit, Bit, Bit)

inputs (i0, i1, i2, i3)

-> Out Bit

output o

The and4 function implements an AND gate explicitly with a LUT4.

and5Source

Arguments

:: (Bit, Bit, Bit, Bit, Bit)

inputs (i0, i1, i2, i3, i4)

-> Out Bit

output o

The and5 function implements an AND gate explicitly with a LUT5.

and6Source

Arguments

:: (Bit, Bit, Bit, Bit, Bit, Bit)

inputs (i0, i1, i2, i3, i4, i5)

-> Out Bit

output o

The and6 function implements an AND gate explicitly with a LUT6.

or2Source

Arguments

:: (Bit, Bit)

inputs (i0, i1)

-> Out Bit

output o

The or2 function implements an OR gate explicitly with a LUT2.

or3Source

Arguments

:: (Bit, Bit, Bit)

inputs (i0, i1, i2)

-> Out Bit

output o

The or3 function implements an AND gate explicitly with a LUT3.

or4Source

Arguments

:: (Bit, Bit, Bit, Bit)

inputs (i0, i1, i2, i3)

-> Out Bit

output o

The or4 function implements an AND gate explicitly with a LUT4.

or5Source

Arguments

:: (Bit, Bit, Bit, Bit, Bit)

inputs (i0, i1, i2, i3, i4)

-> Out Bit

output o

The or5 function implements an AND gate explicitly with a LUT5.

or6Source

Arguments

:: (Bit, Bit, Bit, Bit, Bit, Bit)

inputs (i0, i1, i2, i3, i4, i5)

-> Out Bit

output o

The and6 function implements an AND gate explicitly with a LUT6.

nor2Source

Arguments

:: (Bit, Bit)

inputs (i0, i1)

-> Out Bit

output o

The nor2 function implements an NOR gate explicitly with a LUT2.

xor2Source

Arguments

:: (Bit, Bit)

inputs (i0, i1)

-> Out Bit

output o

The xor2 function implements an XOR gate explicitly with a LUT2.

xnor2Source

Arguments

:: (Bit, Bit)

inputs (i0, i1)

-> Out Bit

output o

The xnor2 function implements an XOR gate explicitly with a LUT2.

muxSource

Arguments

:: (Bit, (Bit, Bit))

inputs (s, (i0, i1))

-> Out Bit

output o

A multiplexor implemented with a LUT3

Carry-chain elements

muxcySource

Arguments

:: (Bit, (Bit, Bit))

(s, (di, ci))

-> Out Bit

o

muxcy_dSource

Arguments

:: Bit

d

-> Bit

ci

-> Bit

di

-> Out (Bit, Bit)

(o, lo)

muxcy_lSource

Arguments

:: Bit

d

-> Bit

ci

-> Bit

di

-> Out (Bit, Bit)

(o, lo)

muxf5Source

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

s

-> Out Bit

o

muxf5_dSource

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

i2

-> Out (Bit, Bit)

(o, lo)

muxf5_lSource

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

i2

-> Out (Bit, Bit)

(o, lo)

muxf6Source

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

s

-> Out Bit

o

muxf6_dSource

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

i2

-> Out (Bit, Bit)

(o, lo)

muxf6_lSource

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

i2

-> Out (Bit, Bit)

(o, lo)

muxf7Source

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

s

-> Out Bit

o

muxf7_dSource

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

i2

-> Out (Bit, Bit)

(o, lo)

muxf7_lSource

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

i2

-> Out (Bit, Bit)

(o, lo)

muxf8Source

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

s

-> Out Bit

o

muxf8_dSource

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

i2

-> Out (Bit, Bit)

(o, lo)

muxf8_lSource

Arguments

:: Bit

i0

-> Bit

i1

-> Bit

i2

-> Out (Bit, Bit)

(o, lo)

xorcySource

Arguments

:: (Bit, Bit)

(li, ci)

-> Out Bit

o

xorcy_dSource

Arguments

:: Bit

ci

-> Bit

di

-> Out (Bit, Bit)

(ci, li)

xorcy_lSource

Arguments

:: Bit

ci

-> Bit

di

-> Out (Bit, Bit)

(ci, li)

Flip-flops

fdSource

Arguments

:: Bit

clk

-> Bit

i

-> Out Bit

q

fdcSource

Arguments

:: Bit

clk

-> Bit 
-> Bit

i

-> Out Bit

q

fdc_1Source

Arguments

:: Bit

clk

-> Bit

clr

-> Bit

i

-> Out Bit

q

fdceSource

Arguments

:: Bit

clk

-> Bit

ce

-> Bit

clr

-> Bit

d

-> Out Bit

q

fdce_1Source

Arguments

:: Bit

clk

-> Bit

ce

-> Bit

clr

-> Bit

d

-> Out Bit

q

fdcpSource

Arguments

:: Bit

clk

-> Bit

clr

-> Bit

pre

-> Bit

d

-> Out Bit

q

fdcpeSource

Arguments

:: Bit

clk

-> Bit

ce

-> Bit

clr

-> Bit

pre

-> Bit

d

-> Out Bit

q

fdcpe_1Source

Arguments

:: Bit

clk

-> Bit

ce

-> Bit

clr

-> Bit

pre

-> Bit

d

-> Out Bit

q

Shift-register primitives

srl16eSource

Arguments

:: Bit

d

-> Bit

clk

-> Bit

ce

-> Bit

a0

-> Bit

a1

-> Bit

a2

-> Bit

a3

-> Out Bit

q

16-bit shift register look-up table with clock enable

Gates implemented in place of a slice latch

and2b1lSource

Arguments

:: Bit

di

-> Bit

sri

-> Out Bit

o

Two input and gate implemented in place of a slice latch

or2lSource

Arguments

:: Bit

di

-> Bit

sri

-> Out Bit

o

Two input and gate implemented in place of a slice latch

Buffers

ibufgSource

Arguments

:: Bit

i

-> Out Bit

o

Dedicated input clock buffer

bufgSource

Arguments

:: Bit

i

-> Out Bit

o

Global clock buffer

bufgpSource

Arguments

:: Bit

i

-> Out Bit

o

Global clock buffer

obufgSource

Arguments

:: Bit

i

-> Out Bit

o

Output buffer

Double data rate (DDR) components

obufdsSource

Arguments

:: Bit

i

-> Out (Bit, Bit)

(o, ob)

Output buffer

Muxing of buses

muxBus :: (Bit, ([Bit], [Bit])) -> Out [Bit]Source

muxBus' :: (Bit, ([Bit], [Bit])) -> Out [Bit]Source

vreg :: Bit -> [Bit] -> Out [Bit]Source

Power and ground

gnd :: Out BitSource

A supply of a constant zero signal.

vcc :: Out BitSource

A supply of a constant one signal.