| 21 | | 1. GHC in registerised mode stores some of its virtual registers in |
| 22 | | real hardware registers for performance. You will need to decide on a |
| 23 | | mapping of GHC's virtual registers to hardware registers. So how |
| 24 | | many registers you want to map and which virtual registers to store |
| 25 | | and where. GHC's design for this on X86 is basically to use as many |
| 26 | | hardware registers as it can and to store the more frequently accessed |
| 27 | | virtual registers like the stack pointer in callee saved registers |
| 28 | | rather than caller saved registers. You can find the mappings that GHC |
| 29 | | currently uses for supported architectures in |
| 30 | | 'includes/stg/MachRegs.h'. |
| | 21 | 1. GHC in registerised mode stores some of its virtual registers in real hardware registers for performance. You will need to decide on a mapping of GHC's virtual registers to hardware registers. So how many registers you want to map and which virtual registers to store and where. GHC's design for this on X86 is basically to use as many hardware registers as it can and to store the more frequently cessed virtual registers like the stack pointer in callee saved registers rather than caller saved registers. You can find the mappings that GHC currently uses for supported architectures in 'includes/stg/MachRegs.h'. |
| 39 | | 4. Add new inline assembly code for your platform to ghc's RTS. See files like |
| 40 | | 'rts/StgCRun.c' that include assembly code for the architectures GHC |
| 41 | | supports. This is the main place as its where the boundary between the |
| 42 | | RTS and haskell code is but I'm sure there are defiantly other places |
| 43 | | that will need to be changed. Just grep the source code to find |
| 44 | | existing assembly and add code for your platform appropriately. |
| | 27 | 4. Add new inline assembly code for your platform to ghc's RTS. See files like 'rts/StgCRun.c' that include assembly code for the architectures GHC supports. This is the main place as its where the boundary between the RTS and haskell code is but I'm sure there are defiantly other places that will need to be changed. Just grep the source code to find existing assembly and add code for your platform appropriately. |
| 48 | | 5.1 'compiler/llvmGen/LlvmCodeGen/Ppr.hs' defines a platform specific |
| 49 | | string that is included in all generated llvm code. Add one for your platform. |
| 50 | | This string specifies the datalayout parameters for the platform (e.g |
| 51 | | pointer size, word size..). If you don't include one llvm should still |
| 52 | | work but wont optimise as aggressively. |
| 53 | | 5.2 'compiler/llvmGen/LlvmCodeGen/CodeGen.hs' has some platform |
| 54 | | specific code on how write barriers should be handled. |
| | 31 | 5.1 'compiler/llvmGen/LlvmCodeGen/Ppr.hs' defines a platform specific string that is included in all generated llvm code. Add one for your platform. This string specifies the datalayout parameters for the platform (e.g pointer size, word size..). If you don't include one llvm should still work but wont optimise as aggressively. |