Ticket #1110 (closed proposed-project: wontfix)
multi-threading for the Cell processor
|Reported by:||malcolm.wallace@…||Owned by:||none|
|Difficulty:||1 person Summer||Mentor:||not-accepted|
Description (last modified by mcatasta) (diff)
IBM's Cell processor architecture consists of a PowerPC processing unit plus eight secondary processing units on the same chip. Each secondary processor has its own separately-addressable on-chip memory, as well as access to main memory through DMA. The secondary processors are connected together with a common bus that is designed for high data throughput.
The hardware architecture immediately suggests a couple of nice possible mappings from Haskell. One idea is that each processor could run a separate function in a composition pipeline, with the compositions themselves being represented simply by communication along the main bus.
Another idea is to allocate explicit concurrent threads amongst the processors, so they run asynchronously apart from communication through MVars. The tricky things here are that (a) the secondary processors have a different instruction set from the main processor, and (b) they have very fast non-shared memory, so separate heaps might be sensible.
- Malcolm Wallace (@ cs.york.ac.uk)
- Michele Catasta <mcatasta@…>