hsverilog-0.1.0: Synthesizable Verilog DSL supporting for multiple clock and reset
HsVerilog.Simulation
val' :: Exp -> Reader Circuit Integer Source
sym' :: Circuit -> Map Text Signal Source
sym :: Circuit -> Text -> Signal Source
val :: Circuit -> Exp -> Integer Source
readReg :: Monad m => Text -> StateT Circuit m Integer Source
readInput :: Monad m => Text -> StateT Circuit m Integer Source
readOutput :: Monad m => Text -> StateT Circuit m Integer Source
readAssign :: Monad m => Text -> StateT Circuit m Integer Source
(<==) :: Monad m => Text -> Integer -> StateT Circuit m () Source
simM :: Monad m => Circuit -> StateT Circuit m a -> m Circuit Source
print' :: MonadIO m => StateT Circuit m () Source
updateReg :: Monad m => StateT Circuit m () Source