Bindings.Libpci.Header

Documentation

c'PCI_VENDOR_ID :: Num a => a

0x00 16 bits

c'PCI_DEVICE_ID :: Num a => a

0x02 16 bits

c'PCI_COMMAND :: Num a => a

0x04 16 bits

c'PCI_COMMAND_IO :: Num a => a

0x1 Enable response in I/O space

c'PCI_COMMAND_MEMORY :: Num a => a

0x2 Enable response in Memory space

c'PCI_COMMAND_MASTER :: Num a => a

0x4 Enable bus mastering

c'PCI_COMMAND_SPECIAL :: Num a => a

0x8 Enable response to special cycles

c'PCI_COMMAND_INVALIDATE :: Num a => a

0x10 Use memory write and invalidate

c'PCI_COMMAND_VGA_PALETTE :: Num a => a

0x20 Enable palette snooping

c'PCI_COMMAND_PARITY :: Num a => a

0x40 Enable parity checking

c'PCI_COMMAND_WAIT :: Num a => a

0x80 Enable address/data stepping

c'PCI_COMMAND_SERR :: Num a => a

0x100 Enable SERR

c'PCI_COMMAND_FAST_BACK :: Num a => a

0x200 Enable back-to-back writes

c'PCI_COMMAND_DISABLE_INTx :: Num a => a

0x400 PCIE: Disable INTx interrupts

c'PCI_STATUS :: Num a => a

0x06 16 bits

c'PCI_STATUS_INTx :: Num a => a

0x08 PCIE: INTx interrupt pending

c'PCI_STATUS_CAP_LIST :: Num a => a

0x10 Support Capability List

c'PCI_STATUS_66MHZ :: Num a => a

0x20 Support 66 Mhz PCI 2.1 bus

c'PCI_STATUS_UDF :: Num a => a

0x40 Support User Definable Features [obsolete]

c'PCI_STATUS_FAST_BACK :: Num a => a

0x80 Accept fast-back to back

c'PCI_STATUS_PARITY :: Num a => a

0x100 Detected parity error

c'PCI_STATUS_DEVSEL_MASK :: Num a => a

c'PCI_STATUS_DEVSEL_FAST :: Num a => a

c'PCI_STATUS_DEVSEL_MEDIUM :: Num a => a

c'PCI_STATUS_DEVSEL_SLOW :: Num a => a

c'PCI_STATUS_SIG_TARGET_ABORT :: Num a => a

c'PCI_STATUS_REC_TARGET_ABORT :: Num a => a

c'PCI_STATUS_REC_MASTER_ABORT :: Num a => a

c'PCI_STATUS_SIG_SYSTEM_ERROR :: Num a => a

c'PCI_STATUS_DETECTED_PARITY :: Num a => a

c'PCI_CLASS_REVISION :: Num a => a

c'PCI_REVISION_ID :: Num a => a

c'PCI_CLASS_PROG :: Num a => a

c'PCI_CLASS_DEVICE :: Num a => a

c'PCI_CACHE_LINE_SIZE :: Num a => a

c'PCI_LATENCY_TIMER :: Num a => a

c'PCI_HEADER_TYPE :: Num a => a

c'PCI_HEADER_TYPE_NORMAL :: Num a => a

c'PCI_HEADER_TYPE_BRIDGE :: Num a => a

c'PCI_HEADER_TYPE_CARDBUS :: Num a => a

c'PCI_BIST :: Num a => a

c'PCI_BIST_CODE_MASK :: Num a => a

c'PCI_BIST_START :: Num a => a

c'PCI_BIST_CAPABLE :: Num a => a

c'PCI_BASE_ADDRESS_0 :: Num a => a

c'PCI_BASE_ADDRESS_1 :: Num a => a

c'PCI_BASE_ADDRESS_2 :: Num a => a

c'PCI_BASE_ADDRESS_3 :: Num a => a

c'PCI_BASE_ADDRESS_4 :: Num a => a

c'PCI_BASE_ADDRESS_5 :: Num a => a

c'PCI_BASE_ADDRESS_SPACE :: Num a => a

c'PCI_BASE_ADDRESS_SPACE_IO :: Num a => a

c'PCI_BASE_ADDRESS_SPACE_MEMORY :: Num a => a

c'PCI_BASE_ADDRESS_MEM_TYPE_MASK :: Num a => a

c'PCI_BASE_ADDRESS_MEM_TYPE_32 :: Num a => a

c'PCI_BASE_ADDRESS_MEM_TYPE_1M :: Num a => a

c'PCI_BASE_ADDRESS_MEM_TYPE_64 :: Num a => a

c'PCI_BASE_ADDRESS_MEM_PREFETCH :: Num a => a

c'PCI_BASE_ADDRESS_MEM_MASK :: Num a => a

c'PCI_BASE_ADDRESS_IO_MASK :: Num a => a

c'PCI_CARDBUS_CIS :: Num a => a

c'PCI_SUBSYSTEM_VENDOR_ID :: Num a => a

c'PCI_SUBSYSTEM_ID :: Num a => a

c'PCI_ROM_ADDRESS :: Num a => a

c'PCI_ROM_ADDRESS_ENABLE :: Num a => a

c'PCI_ROM_ADDRESS_MASK :: Num a => a

c'PCI_CAPABILITY_LIST :: Num a => a

c'PCI_INTERRUPT_LINE :: Num a => a

c'PCI_INTERRUPT_PIN :: Num a => a

c'PCI_MIN_GNT :: Num a => a

c'PCI_MAX_LAT :: Num a => a

c'PCI_PRIMARY_BUS :: Num a => a

c'PCI_SECONDARY_BUS :: Num a => a

c'PCI_SUBORDINATE_BUS :: Num a => a

c'PCI_SEC_LATENCY_TIMER :: Num a => a

c'PCI_IO_BASE :: Num a => a

c'PCI_IO_LIMIT :: Num a => a

c'PCI_IO_RANGE_TYPE_MASK :: Num a => a

c'PCI_IO_RANGE_TYPE_16 :: Num a => a

c'PCI_IO_RANGE_TYPE_32 :: Num a => a

c'PCI_IO_RANGE_MASK :: Num a => a

c'PCI_SEC_STATUS :: Num a => a

c'PCI_MEMORY_BASE :: Num a => a

c'PCI_MEMORY_LIMIT :: Num a => a

c'PCI_MEMORY_RANGE_TYPE_MASK :: Num a => a

c'PCI_MEMORY_RANGE_MASK :: Num a => a

c'PCI_PREF_MEMORY_BASE :: Num a => a

c'PCI_PREF_MEMORY_LIMIT :: Num a => a

c'PCI_PREF_RANGE_TYPE_MASK :: Num a => a

c'PCI_PREF_RANGE_TYPE_32 :: Num a => a

c'PCI_PREF_RANGE_TYPE_64 :: Num a => a

c'PCI_PREF_RANGE_MASK :: Num a => a

c'PCI_PREF_BASE_UPPER32 :: Num a => a

c'PCI_PREF_LIMIT_UPPER32 :: Num a => a

c'PCI_IO_BASE_UPPER16 :: Num a => a

c'PCI_IO_LIMIT_UPPER16 :: Num a => a

c'PCI_ROM_ADDRESS1 :: Num a => a

c'PCI_BRIDGE_CONTROL :: Num a => a

c'PCI_BRIDGE_CTL_PARITY :: Num a => a

c'PCI_BRIDGE_CTL_SERR :: Num a => a

c'PCI_BRIDGE_CTL_NO_ISA :: Num a => a

c'PCI_BRIDGE_CTL_VGA :: Num a => a

c'PCI_BRIDGE_CTL_MASTER_ABORT :: Num a => a

c'PCI_BRIDGE_CTL_BUS_RESET :: Num a => a

c'PCI_BRIDGE_CTL_FAST_BACK :: Num a => a

c'PCI_BRIDGE_CTL_PRI_DISCARD_TIMER :: Num a => a

c'PCI_BRIDGE_CTL_SEC_DISCARD_TIMER :: Num a => a

c'PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS :: Num a => a

c'PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN :: Num a => a

c'PCI_CB_CAPABILITY_LIST :: Num a => a

c'PCI_CB_SEC_STATUS :: Num a => a

c'PCI_CB_PRIMARY_BUS :: Num a => a

c'PCI_CB_CARD_BUS :: Num a => a

c'PCI_CB_SUBORDINATE_BUS :: Num a => a

c'PCI_CB_LATENCY_TIMER :: Num a => a

c'PCI_CB_MEMORY_BASE_0 :: Num a => a

c'PCI_CB_MEMORY_LIMIT_0 :: Num a => a

c'PCI_CB_MEMORY_BASE_1 :: Num a => a

c'PCI_CB_MEMORY_LIMIT_1 :: Num a => a

c'PCI_CB_IO_BASE_0 :: Num a => a

c'PCI_CB_IO_BASE_0_HI :: Num a => a

c'PCI_CB_IO_LIMIT_0 :: Num a => a

c'PCI_CB_IO_LIMIT_0_HI :: Num a => a

c'PCI_CB_IO_BASE_1 :: Num a => a

c'PCI_CB_IO_BASE_1_HI :: Num a => a

c'PCI_CB_IO_LIMIT_1 :: Num a => a

c'PCI_CB_IO_LIMIT_1_HI :: Num a => a

c'PCI_CB_IO_RANGE_MASK :: Num a => a

c'PCI_CB_BRIDGE_CONTROL :: Num a => a

c'PCI_CB_BRIDGE_CTL_PARITY :: Num a => a

c'PCI_CB_BRIDGE_CTL_SERR :: Num a => a

c'PCI_CB_BRIDGE_CTL_ISA :: Num a => a

c'PCI_CB_BRIDGE_CTL_VGA :: Num a => a

c'PCI_CB_BRIDGE_CTL_MASTER_ABORT :: Num a => a

c'PCI_CB_BRIDGE_CTL_CB_RESET :: Num a => a

c'PCI_CB_BRIDGE_CTL_16BIT_INT :: Num a => a

c'PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 :: Num a => a

c'PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 :: Num a => a

c'PCI_CB_BRIDGE_CTL_POST_WRITES :: Num a => a

c'PCI_CB_SUBSYSTEM_VENDOR_ID :: Num a => a

c'PCI_CB_SUBSYSTEM_ID :: Num a => a

c'PCI_CB_LEGACY_MODE_BASE :: Num a => a

c'PCI_CAP_LIST_ID :: Num a => a

c'PCI_CAP_ID_PM :: Num a => a

c'PCI_CAP_ID_AGP :: Num a => a

c'PCI_CAP_ID_VPD :: Num a => a

c'PCI_CAP_ID_SLOTID :: Num a => a

c'PCI_CAP_ID_MSI :: Num a => a

c'PCI_CAP_ID_CHSWP :: Num a => a

c'PCI_CAP_ID_PCIX :: Num a => a

c'PCI_CAP_ID_HT :: Num a => a

c'PCI_CAP_ID_VNDR :: Num a => a

c'PCI_CAP_ID_DBG :: Num a => a

c'PCI_CAP_ID_CCRC :: Num a => a

c'PCI_CAP_ID_HOTPLUG :: Num a => a

c'PCI_CAP_ID_SSVID :: Num a => a

c'PCI_CAP_ID_AGP3 :: Num a => a

c'PCI_CAP_ID_SECURE :: Num a => a

c'PCI_CAP_ID_EXP :: Num a => a

c'PCI_CAP_ID_MSIX :: Num a => a

c'PCI_CAP_ID_SATA :: Num a => a

c'PCI_CAP_ID_AF :: Num a => a

c'PCI_CAP_ID_EA :: Num a => a

c'PCI_CAP_LIST_NEXT :: Num a => a

c'PCI_CAP_FLAGS :: Num a => a

c'PCI_CAP_SIZEOF :: Num a => a

c'PCI_EXT_CAP_ID_AER :: Num a => a

c'PCI_EXT_CAP_ID_VC :: Num a => a

c'PCI_EXT_CAP_ID_DSN :: Num a => a

c'PCI_EXT_CAP_ID_PB :: Num a => a

c'PCI_EXT_CAP_ID_RCLINK :: Num a => a

c'PCI_EXT_CAP_ID_RCILINK :: Num a => a

c'PCI_EXT_CAP_ID_RCECOLL :: Num a => a

c'PCI_EXT_CAP_ID_MFVC :: Num a => a

c'PCI_EXT_CAP_ID_VC2 :: Num a => a

c'PCI_EXT_CAP_ID_VNDR :: Num a => a

c'PCI_EXT_CAP_ID_ACS :: Num a => a

c'PCI_EXT_CAP_ID_ARI :: Num a => a

c'PCI_EXT_CAP_ID_ATS :: Num a => a

c'PCI_EXT_CAP_ID_SRIOV :: Num a => a

c'PCI_EXT_CAP_ID_PRI :: Num a => a

c'PCI_EXT_CAP_ID_TPH :: Num a => a

c'PCI_EXT_CAP_ID_LTR :: Num a => a

c'PCI_EXT_CAP_ID_PASID :: Num a => a

c'PCI_EXT_CAP_ID_DPC :: Num a => a

c'PCI_EXT_CAP_ID_L1PM :: Num a => a

c'PCI_EXT_CAP_ID_PTM :: Num a => a

c'PCI_PM_CAP_VER_MASK :: Num a => a

c'PCI_PM_CAP_PME_CLOCK :: Num a => a

c'PCI_PM_CAP_DSI :: Num a => a

c'PCI_PM_CAP_AUX_C_MASK :: Num a => a

c'PCI_PM_CAP_D1 :: Num a => a

c'PCI_PM_CAP_D2 :: Num a => a

c'PCI_PM_CAP_PME_D0 :: Num a => a

c'PCI_PM_CAP_PME_D1 :: Num a => a

c'PCI_PM_CAP_PME_D2 :: Num a => a

c'PCI_PM_CAP_PME_D3_HOT :: Num a => a

c'PCI_PM_CAP_PME_D3_COLD :: Num a => a

c'PCI_PM_CTRL :: Num a => a

c'PCI_PM_CTRL_STATE_MASK :: Num a => a

c'PCI_PM_CTRL_NO_SOFT_RST :: Num a => a

c'PCI_PM_CTRL_PME_ENABLE :: Num a => a

c'PCI_PM_CTRL_DATA_SEL_MASK :: Num a => a

c'PCI_PM_CTRL_DATA_SCALE_MASK :: Num a => a

c'PCI_PM_CTRL_PME_STATUS :: Num a => a

c'PCI_PM_PPB_EXTENSIONS :: Num a => a

c'PCI_PM_PPB_B2_B3 :: Num a => a

c'PCI_PM_BPCC_ENABLE :: Num a => a

c'PCI_PM_DATA_REGISTER :: Num a => a

c'PCI_PM_SIZEOF :: Num a => a

c'PCI_AGP_VERSION :: Num a => a

c'PCI_AGP_RFU :: Num a => a

c'PCI_AGP_STATUS :: Num a => a

c'PCI_AGP_STATUS_RQ_MASK :: Num a => a

c'PCI_AGP_STATUS_ISOCH :: Num a => a

c'PCI_AGP_STATUS_ARQSZ_MASK :: Num a => a

c'PCI_AGP_STATUS_CAL_MASK :: Num a => a

c'PCI_AGP_STATUS_SBA :: Num a => a

c'PCI_AGP_STATUS_ITA_COH :: Num a => a

c'PCI_AGP_STATUS_GART64 :: Num a => a

c'PCI_AGP_STATUS_HTRANS :: Num a => a

c'PCI_AGP_STATUS_64BIT :: Num a => a

c'PCI_AGP_STATUS_FW :: Num a => a

c'PCI_AGP_STATUS_AGP3 :: Num a => a

c'PCI_AGP_STATUS_RATE4 :: Num a => a

c'PCI_AGP_STATUS_RATE2 :: Num a => a

c'PCI_AGP_STATUS_RATE1 :: Num a => a

c'PCI_AGP_COMMAND :: Num a => a

c'PCI_AGP_COMMAND_RQ_MASK :: Num a => a

c'PCI_AGP_COMMAND_ARQSZ_MASK :: Num a => a

c'PCI_AGP_COMMAND_CAL_MASK :: Num a => a

c'PCI_AGP_COMMAND_SBA :: Num a => a

c'PCI_AGP_COMMAND_AGP :: Num a => a

c'PCI_AGP_COMMAND_GART64 :: Num a => a

c'PCI_AGP_COMMAND_64BIT :: Num a => a

c'PCI_AGP_COMMAND_FW :: Num a => a

c'PCI_AGP_COMMAND_RATE4 :: Num a => a

c'PCI_AGP_COMMAND_RATE2 :: Num a => a

c'PCI_AGP_COMMAND_RATE1 :: Num a => a

c'PCI_AGP_SIZEOF :: Num a => a

c'PCI_VPD_ADDR :: Num a => a

c'PCI_VPD_ADDR_MASK :: Num a => a

c'PCI_VPD_ADDR_F :: Num a => a

c'PCI_VPD_DATA :: Num a => a

c'PCI_SID_ESR :: Num a => a

c'PCI_SID_ESR_NSLOTS :: Num a => a

c'PCI_SID_ESR_FIC :: Num a => a

c'PCI_SID_CHASSIS_NR :: Num a => a

c'PCI_MSI_FLAGS :: Num a => a

c'PCI_MSI_FLAGS_MASK_BIT :: Num a => a

c'PCI_MSI_FLAGS_64BIT :: Num a => a

c'PCI_MSI_FLAGS_QSIZE :: Num a => a

c'PCI_MSI_FLAGS_QMASK :: Num a => a

c'PCI_MSI_FLAGS_ENABLE :: Num a => a

c'PCI_MSI_RFU :: Num a => a

c'PCI_MSI_ADDRESS_LO :: Num a => a

c'PCI_MSI_ADDRESS_HI :: Num a => a

c'PCI_MSI_DATA_32 :: Num a => a

c'PCI_MSI_DATA_64 :: Num a => a

c'PCI_MSI_MASK_BIT_32 :: Num a => a

c'PCI_MSI_MASK_BIT_64 :: Num a => a

c'PCI_MSI_PENDING_32 :: Num a => a

c'PCI_MSI_PENDING_64 :: Num a => a

c'PCI_PCIX_COMMAND :: Num a => a

c'PCI_PCIX_COMMAND_DPERE :: Num a => a

c'PCI_PCIX_COMMAND_ERO :: Num a => a

c'PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT :: Num a => a

c'PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS :: Num a => a

c'PCI_PCIX_COMMAND_RESERVED :: Num a => a

c'PCI_PCIX_STATUS :: Num a => a

c'PCI_PCIX_STATUS_FUNCTION :: Num a => a

c'PCI_PCIX_STATUS_DEVICE :: Num a => a

c'PCI_PCIX_STATUS_BUS :: Num a => a

c'PCI_PCIX_STATUS_64BIT :: Num a => a

c'PCI_PCIX_STATUS_133MHZ :: Num a => a

c'PCI_PCIX_STATUS_SC_DISCARDED :: Num a => a

c'PCI_PCIX_STATUS_UNEXPECTED_SC :: Num a => a

c'PCI_PCIX_STATUS_DEVICE_COMPLEXITY :: Num a => a

c'PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT :: Num a => a

c'PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS :: Num a => a

c'PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE :: Num a => a

c'PCI_PCIX_STATUS_RCVD_SC_ERR_MESS :: Num a => a

c'PCI_PCIX_STATUS_266MHZ :: Num a => a

c'PCI_PCIX_STATUS_533MHZ :: Num a => a

c'PCI_PCIX_SIZEOF :: Num a => a

c'PCI_PCIX_BRIDGE_SEC_STATUS :: Num a => a

c'PCI_PCIX_BRIDGE_SEC_STATUS_64BIT :: Num a => a

c'PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ :: Num a => a

c'PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED :: Num a => a

c'PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC :: Num a => a

c'PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN :: Num a => a

c'PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED :: Num a => a

c'PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ :: Num a => a

c'PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS_FUNCTION :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS_DEVICE :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS_BUS :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS_64BIT :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS_133MHZ :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED :: Num a => a

c'PCI_PCIX_BRIDGE_STATUS_RESERVED :: Num a => a

c'PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL :: Num a => a

c'PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL :: Num a => a

c'PCI_PCIX_BRIDGE_STR_CAPACITY :: Num a => a

c'PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT :: Num a => a

c'PCI_PCIX_BRIDGE_SIZEOF :: Num a => a

c'PCI_HT_CMD :: Num a => a

c'PCI_HT_CMD_TYP_HI :: Num a => a

c'PCI_HT_CMD_TYP_HI_PRI :: Num a => a

c'PCI_HT_CMD_TYP_HI_SEC :: Num a => a

c'PCI_HT_CMD_TYP :: Num a => a

c'PCI_HT_CMD_TYP_SW :: Num a => a

c'PCI_HT_CMD_TYP_IDC :: Num a => a

c'PCI_HT_CMD_TYP_RID :: Num a => a

c'PCI_HT_CMD_TYP_UIDC :: Num a => a

c'PCI_HT_CMD_TYP_ECSA :: Num a => a

c'PCI_HT_CMD_TYP_AM :: Num a => a

c'PCI_HT_CMD_TYP_MSIM :: Num a => a

c'PCI_HT_CMD_TYP_DR :: Num a => a

c'PCI_HT_CMD_TYP_VCS :: Num a => a

c'PCI_HT_CMD_TYP_RM :: Num a => a

c'PCI_HT_CMD_TYP_X86 :: Num a => a

c'PCI_HT_LCTR_CFLE :: Num a => a

c'PCI_HT_LCTR_CST :: Num a => a

c'PCI_HT_LCTR_CFE :: Num a => a

c'PCI_HT_LCTR_LKFAIL :: Num a => a

c'PCI_HT_LCTR_INIT :: Num a => a

c'PCI_HT_LCTR_EOC :: Num a => a

c'PCI_HT_LCTR_TXO :: Num a => a

c'PCI_HT_LCTR_CRCERR :: Num a => a

c'PCI_HT_LCTR_ISOCEN :: Num a => a

c'PCI_HT_LCTR_LSEN :: Num a => a

c'PCI_HT_LCTR_EXTCTL :: Num a => a

c'PCI_HT_LCTR_64B :: Num a => a

c'PCI_HT_LCNF_MLWI :: Num a => a

c'PCI_HT_LCNF_LW_8B :: Num a => a

c'PCI_HT_LCNF_LW_16B :: Num a => a

c'PCI_HT_LCNF_LW_32B :: Num a => a

c'PCI_HT_LCNF_LW_2B :: Num a => a

c'PCI_HT_LCNF_LW_4B :: Num a => a

c'PCI_HT_LCNF_LW_NC :: Num a => a

c'PCI_HT_LCNF_DFI :: Num a => a

c'PCI_HT_LCNF_MLWO :: Num a => a

c'PCI_HT_LCNF_DFO :: Num a => a

c'PCI_HT_LCNF_LWI :: Num a => a

c'PCI_HT_LCNF_DFIE :: Num a => a

c'PCI_HT_LCNF_LWO :: Num a => a

c'PCI_HT_LCNF_DFOE :: Num a => a

c'PCI_HT_RID_MIN :: Num a => a

c'PCI_HT_RID_MAJ :: Num a => a

c'PCI_HT_LFRER_FREQ :: Num a => a

c'PCI_HT_LFRER_200 :: Num a => a

c'PCI_HT_LFRER_300 :: Num a => a

c'PCI_HT_LFRER_400 :: Num a => a

c'PCI_HT_LFRER_500 :: Num a => a

c'PCI_HT_LFRER_600 :: Num a => a

c'PCI_HT_LFRER_800 :: Num a => a

c'PCI_HT_LFRER_1000 :: Num a => a

c'PCI_HT_LFRER_1200 :: Num a => a

c'PCI_HT_LFRER_1400 :: Num a => a

c'PCI_HT_LFRER_1600 :: Num a => a

c'PCI_HT_LFRER_VEND :: Num a => a

c'PCI_HT_LFRER_ERR :: Num a => a

c'PCI_HT_LFRER_PROT :: Num a => a

c'PCI_HT_LFRER_OV :: Num a => a

c'PCI_HT_LFRER_EOC :: Num a => a

c'PCI_HT_LFRER_CTLT :: Num a => a

c'PCI_HT_LFCAP_200 :: Num a => a

c'PCI_HT_LFCAP_300 :: Num a => a

c'PCI_HT_LFCAP_400 :: Num a => a

c'PCI_HT_LFCAP_500 :: Num a => a

c'PCI_HT_LFCAP_600 :: Num a => a

c'PCI_HT_LFCAP_800 :: Num a => a

c'PCI_HT_LFCAP_1000 :: Num a => a

c'PCI_HT_LFCAP_1200 :: Num a => a

c'PCI_HT_LFCAP_1400 :: Num a => a

c'PCI_HT_LFCAP_1600 :: Num a => a

c'PCI_HT_LFCAP_VEND :: Num a => a

c'PCI_HT_FTR_ISOCFC :: Num a => a

c'PCI_HT_FTR_LDTSTOP :: Num a => a

c'PCI_HT_FTR_CRCTM :: Num a => a

c'PCI_HT_FTR_ECTLT :: Num a => a

c'PCI_HT_FTR_64BA :: Num a => a

c'PCI_HT_FTR_UIDRD :: Num a => a

c'PCI_HT_EH_PFLE :: Num a => a

c'PCI_HT_EH_OFLE :: Num a => a

c'PCI_HT_EH_PFE :: Num a => a

c'PCI_HT_EH_OFE :: Num a => a

c'PCI_HT_EH_EOCFE :: Num a => a

c'PCI_HT_EH_RFE :: Num a => a

c'PCI_HT_EH_CRCFE :: Num a => a

c'PCI_HT_EH_SERRFE :: Num a => a

c'PCI_HT_EH_CF :: Num a => a

c'PCI_HT_EH_RE :: Num a => a

c'PCI_HT_EH_PNFE :: Num a => a

c'PCI_HT_EH_ONFE :: Num a => a

c'PCI_HT_EH_EOCNFE :: Num a => a

c'PCI_HT_EH_RNFE :: Num a => a

c'PCI_HT_EH_CRCNFE :: Num a => a

c'PCI_HT_EH_SERRNFE :: Num a => a

c'PCI_HT_PRI_CMD :: Num a => a

c'PCI_HT_PRI_CMD_BUID :: Num a => a

c'PCI_HT_PRI_CMD_UC :: Num a => a

c'PCI_HT_PRI_CMD_MH :: Num a => a

c'PCI_HT_PRI_CMD_DD :: Num a => a

c'PCI_HT_PRI_CMD_DUL :: Num a => a

c'PCI_HT_PRI_LCTR0 :: Num a => a

c'PCI_HT_PRI_LCNF0 :: Num a => a

c'PCI_HT_PRI_LCTR1 :: Num a => a

c'PCI_HT_PRI_LCNF1 :: Num a => a

c'PCI_HT_PRI_RID :: Num a => a

c'PCI_HT_PRI_LFRER0 :: Num a => a

c'PCI_HT_PRI_LFCAP0 :: Num a => a

c'PCI_HT_PRI_FTR :: Num a => a

c'PCI_HT_PRI_LFRER1 :: Num a => a

c'PCI_HT_PRI_LFCAP1 :: Num a => a

c'PCI_HT_PRI_ES :: Num a => a

c'PCI_HT_PRI_EH :: Num a => a

c'PCI_HT_PRI_MBU :: Num a => a

c'PCI_HT_PRI_MLU :: Num a => a

c'PCI_HT_PRI_BN :: Num a => a

c'PCI_HT_PRI_SIZEOF :: Num a => a

c'PCI_HT_SEC_CMD :: Num a => a

c'PCI_HT_SEC_CMD_WR :: Num a => a

c'PCI_HT_SEC_CMD_DE :: Num a => a

c'PCI_HT_SEC_CMD_DN :: Num a => a

c'PCI_HT_SEC_CMD_CS :: Num a => a

c'PCI_HT_SEC_CMD_HH :: Num a => a

c'PCI_HT_SEC_CMD_AS :: Num a => a

c'PCI_HT_SEC_CMD_HIECE :: Num a => a

c'PCI_HT_SEC_CMD_DUL :: Num a => a

c'PCI_HT_SEC_LCTR :: Num a => a

c'PCI_HT_SEC_LCNF :: Num a => a

c'PCI_HT_SEC_RID :: Num a => a

c'PCI_HT_SEC_LFRER :: Num a => a

c'PCI_HT_SEC_LFCAP :: Num a => a

c'PCI_HT_SEC_FTR :: Num a => a

c'PCI_HT_SEC_FTR_EXTRS :: Num a => a

c'PCI_HT_SEC_FTR_UCNFE :: Num a => a

c'PCI_HT_SEC_ES :: Num a => a

c'PCI_HT_SEC_EH :: Num a => a

c'PCI_HT_SEC_MBU :: Num a => a

c'PCI_HT_SEC_MLU :: Num a => a

c'PCI_HT_SEC_SIZEOF :: Num a => a

c'PCI_HT_SW_CMD :: Num a => a

c'PCI_HT_SW_CMD_VIBERR :: Num a => a

c'PCI_HT_SW_CMD_VIBFL :: Num a => a

c'PCI_HT_SW_CMD_VIBFT :: Num a => a

c'PCI_HT_SW_CMD_VIBNFT :: Num a => a

c'PCI_HT_SW_PMASK :: Num a => a

c'PCI_HT_SW_SWINF :: Num a => a

c'PCI_HT_SW_SWINF_DP :: Num a => a

c'PCI_HT_SW_SWINF_EN :: Num a => a

c'PCI_HT_SW_SWINF_CR :: Num a => a

c'PCI_HT_SW_SWINF_PCIDX :: Num a => a

c'PCI_HT_SW_SWINF_BLRIDX :: Num a => a

c'PCI_HT_SW_SWINF_SBIDX :: Num a => a

c'PCI_HT_SW_SWINF_HP :: Num a => a

c'PCI_HT_SW_SWINF_HIDE :: Num a => a

c'PCI_HT_SW_PCD :: Num a => a

c'PCI_HT_SW_BLRD :: Num a => a

c'PCI_HT_SW_SBD :: Num a => a

c'PCI_HT_SW_SIZEOF :: Num a => a

c'PCI_HT_SW_PC_PCR :: Num a => a

c'PCI_HT_SW_PC_NPCR :: Num a => a

c'PCI_HT_SW_PC_RCR :: Num a => a

c'PCI_HT_SW_PC_PDWR :: Num a => a

c'PCI_HT_SW_PC_NPDWR :: Num a => a

c'PCI_HT_SW_PC_RDWR :: Num a => a

c'PCI_HT_SW_PC_PCT :: Num a => a

c'PCI_HT_SW_PC_NPCT :: Num a => a

c'PCI_HT_SW_PC_RCT :: Num a => a

c'PCI_HT_SW_PC_PDWT :: Num a => a

c'PCI_HT_SW_PC_NPDWT :: Num a => a

c'PCI_HT_SW_PC_RDWT :: Num a => a

c'PCI_HT_SW_BLR_BASE0_LO :: Num a => a

c'PCI_HT_SW_BLR_BASE0_HI :: Num a => a

c'PCI_HT_SW_BLR_LIM0_LO :: Num a => a

c'PCI_HT_SW_BLR_LIM0_HI :: Num a => a

c'PCI_HT_SW_SB_LO :: Num a => a

c'PCI_HT_SW_S0_HI :: Num a => a

c'PCI_HT_IDC_IDX :: Num a => a

c'PCI_HT_IDC_DATA :: Num a => a

c'PCI_HT_IDC_SIZEOF :: Num a => a

c'PCI_HT_IDC_IDX_LINT :: Num a => a

c'PCI_HT_IDC_LINT :: Num a => a

c'PCI_HT_IDC_IDX_IDR :: Num a => a

c'PCI_HT_IDC_IDR_MASK :: Num a => a

c'PCI_HT_IDC_IDR_POL :: Num a => a

c'PCI_HT_IDC_IDR_II_2 :: Num a => a

c'PCI_HT_IDC_IDR_II_5 :: Num a => a

c'PCI_HT_IDC_IDR_II_6 :: Num a => a

c'PCI_HT_IDC_IDR_II_24 :: Num a => a

c'PCI_HT_IDC_IDR_II_32 :: Num a => a

c'PCI_HT_IDC_IDR_PASSPW :: Num a => a

c'PCI_HT_IDC_IDR_WEOI :: Num a => a

c'PCI_HT_RID_RID :: Num a => a

c'PCI_HT_RID_SIZEOF :: Num a => a

c'PCI_HT_UIDC_CS :: Num a => a

c'PCI_HT_UIDC_CE :: Num a => a

c'PCI_HT_UIDC_SIZEOF :: Num a => a

c'PCI_HT_ECSA_ADDR :: Num a => a

c'PCI_HT_ECSA_ADDR_REG :: Num a => a

c'PCI_HT_ECSA_ADDR_FUN :: Num a => a

c'PCI_HT_ECSA_ADDR_DEV :: Num a => a

c'PCI_HT_ECSA_ADDR_BUS :: Num a => a

c'PCI_HT_ECSA_ADDR_TYPE :: Num a => a

c'PCI_HT_ECSA_DATA :: Num a => a

c'PCI_HT_ECSA_SIZEOF :: Num a => a

c'PCI_HT_AM_CMD :: Num a => a

c'PCI_HT_AM_CMD_NDMA :: Num a => a

c'PCI_HT_AM_CMD_IOSIZ :: Num a => a

c'PCI_HT_AM_CMD_MT :: Num a => a

c'PCI_HT_AM_CMD_MT_40B :: Num a => a

c'PCI_HT_AM_CMD_MT_64B :: Num a => a

c'PCI_HT_AM_SBW_CTR_COMP :: Num a => a

c'PCI_HT_AM_SBW_CTR_NCOH :: Num a => a

c'PCI_HT_AM_SBW_CTR_ISOC :: Num a => a

c'PCI_HT_AM_SBW_CTR_EN :: Num a => a

c'PCI_HT_AM40_SBNPW :: Num a => a

c'PCI_HT_AM40_SBW_BASE :: Num a => a

c'PCI_HT_AM40_SBW_CTR :: Num a => a

c'PCI_HT_AM40_SBPW :: Num a => a

c'PCI_HT_AM40_DMA_PBASE0 :: Num a => a

c'PCI_HT_AM40_DMA_CTR0 :: Num a => a

c'PCI_HT_AM40_DMA_CTR_CTR :: Num a => a

c'PCI_HT_AM40_DMA_SLIM0 :: Num a => a

c'PCI_HT_AM40_DMA_SBASE0 :: Num a => a

c'PCI_HT_AM40_SIZEOF :: Num a => a

c'PCI_HT_AM64_IDX :: Num a => a

c'PCI_HT_AM64_DATA_LO :: Num a => a

c'PCI_HT_AM64_DATA_HI :: Num a => a

c'PCI_HT_AM64_SIZEOF :: Num a => a

c'PCI_HT_AM64_IDX_SBNPW :: Num a => a

c'PCI_HT_AM64_W_BASE_LO :: Num a => a

c'PCI_HT_AM64_W_CTR :: Num a => a

c'PCI_HT_AM64_IDX_SBPW :: Num a => a

c'PCI_HT_AM64_IDX_PBNPW :: Num a => a

c'PCI_HT_AM64_IDX_DMAPB0 :: Num a => a

c'PCI_HT_AM64_IDX_DMASB0 :: Num a => a

c'PCI_HT_AM64_IDX_DMASL0 :: Num a => a

c'PCI_HT_MSIM_CMD :: Num a => a

c'PCI_HT_MSIM_CMD_EN :: Num a => a

c'PCI_HT_MSIM_CMD_FIXD :: Num a => a

c'PCI_HT_MSIM_ADDR_LO :: Num a => a

c'PCI_HT_MSIM_ADDR_HI :: Num a => a

c'PCI_HT_MSIM_SIZEOF :: Num a => a

c'PCI_HT_DR_CMD :: Num a => a

c'PCI_HT_DR_CMD_NDRS :: Num a => a

c'PCI_HT_DR_CMD_IDX :: Num a => a

c'PCI_HT_DR_EN :: Num a => a

c'PCI_HT_DR_DATA :: Num a => a

c'PCI_HT_DR_SIZEOF :: Num a => a

c'PCI_HT_DR_IDX_BASE_LO :: Num a => a

c'PCI_HT_DR_OTNRD :: Num a => a

c'PCI_HT_DR_BL_LO :: Num a => a

c'PCI_HT_DR_IDX_BASE_HI :: Num a => a

c'PCI_HT_DR_IDX_LIMIT_LO :: Num a => a

c'PCI_HT_DR_IDX_LIMIT_HI :: Num a => a

c'PCI_HT_VCS_SUP :: Num a => a

c'PCI_HT_VCS_L1EN :: Num a => a

c'PCI_HT_VCS_L0EN :: Num a => a

c'PCI_HT_VCS_SBD :: Num a => a

c'PCI_HT_VCS_SINT :: Num a => a

c'PCI_HT_VCS_SSUP :: Num a => a

c'PCI_HT_VCS_SSUP_0 :: Num a => a

c'PCI_HT_VCS_SSUP_3 :: Num a => a

c'PCI_HT_VCS_SSUP_15 :: Num a => a

c'PCI_HT_VCS_NFCBD :: Num a => a

c'PCI_HT_VCS_NFCINT :: Num a => a

c'PCI_HT_VCS_SIZEOF :: Num a => a

c'PCI_HT_RM_CTR0 :: Num a => a

c'PCI_HT_RM_CTR_LRETEN :: Num a => a

c'PCI_HT_RM_CTR_FSER :: Num a => a

c'PCI_HT_RM_CTR_ROLNEN :: Num a => a

c'PCI_HT_RM_CTR_FSS :: Num a => a

c'PCI_HT_RM_CTR_RETNEN :: Num a => a

c'PCI_HT_RM_CTR_RETFEN :: Num a => a

c'PCI_HT_RM_CTR_AA :: Num a => a

c'PCI_HT_RM_STS0 :: Num a => a

c'PCI_HT_RM_STS_RETSNT :: Num a => a

c'PCI_HT_RM_STS_CNTROL :: Num a => a

c'PCI_HT_RM_STS_SRCV :: Num a => a

c'PCI_HT_RM_CTR1 :: Num a => a

c'PCI_HT_RM_STS1 :: Num a => a

c'PCI_HT_RM_CNT0 :: Num a => a

c'PCI_HT_RM_CNT1 :: Num a => a

c'PCI_HT_RM_SIZEOF :: Num a => a

c'PCI_VNDR_LENGTH :: Num a => a

c'PCI_EXP_FLAGS :: Num a => a

c'PCI_EXP_FLAGS_VERS :: Num a => a

c'PCI_EXP_FLAGS_TYPE :: Num a => a

c'PCI_EXP_TYPE_ENDPOINT :: Num a => a

c'PCI_EXP_TYPE_LEG_END :: Num a => a

c'PCI_EXP_TYPE_ROOT_PORT :: Num a => a

c'PCI_EXP_TYPE_UPSTREAM :: Num a => a

c'PCI_EXP_TYPE_DOWNSTREAM :: Num a => a

c'PCI_EXP_TYPE_PCI_BRIDGE :: Num a => a

c'PCI_EXP_TYPE_PCIE_BRIDGE :: Num a => a

c'PCI_EXP_TYPE_ROOT_INT_EP :: Num a => a

c'PCI_EXP_TYPE_ROOT_EC :: Num a => a

c'PCI_EXP_FLAGS_SLOT :: Num a => a

c'PCI_EXP_FLAGS_IRQ :: Num a => a

c'PCI_EXP_DEVCAP :: Num a => a

c'PCI_EXP_DEVCAP_PAYLOAD :: Num a => a

c'PCI_EXP_DEVCAP_PHANTOM :: Num a => a

c'PCI_EXP_DEVCAP_EXT_TAG :: Num a => a

c'PCI_EXP_DEVCAP_L0S :: Num a => a

c'PCI_EXP_DEVCAP_L1 :: Num a => a

c'PCI_EXP_DEVCAP_ATN_BUT :: Num a => a

c'PCI_EXP_DEVCAP_ATN_IND :: Num a => a

c'PCI_EXP_DEVCAP_PWR_IND :: Num a => a

c'PCI_EXP_DEVCAP_RBE :: Num a => a

c'PCI_EXP_DEVCAP_PWR_VAL :: Num a => a

c'PCI_EXP_DEVCAP_PWR_SCL :: Num a => a

c'PCI_EXP_DEVCAP_FLRESET :: Num a => a

c'PCI_EXP_DEVCTL :: Num a => a

c'PCI_EXP_DEVCTL_CERE :: Num a => a

c'PCI_EXP_DEVCTL_NFERE :: Num a => a

c'PCI_EXP_DEVCTL_FERE :: Num a => a

c'PCI_EXP_DEVCTL_URRE :: Num a => a

c'PCI_EXP_DEVCTL_RELAXED :: Num a => a

c'PCI_EXP_DEVCTL_PAYLOAD :: Num a => a

c'PCI_EXP_DEVCTL_EXT_TAG :: Num a => a

c'PCI_EXP_DEVCTL_PHANTOM :: Num a => a

c'PCI_EXP_DEVCTL_AUX_PME :: Num a => a

c'PCI_EXP_DEVCTL_NOSNOOP :: Num a => a

c'PCI_EXP_DEVCTL_READRQ :: Num a => a

c'PCI_EXP_DEVCTL_BCRE :: Num a => a

c'PCI_EXP_DEVCTL_FLRESET :: Num a => a

c'PCI_EXP_DEVSTA :: Num a => a

c'PCI_EXP_DEVSTA_CED :: Num a => a

c'PCI_EXP_DEVSTA_NFED :: Num a => a

c'PCI_EXP_DEVSTA_FED :: Num a => a

c'PCI_EXP_DEVSTA_URD :: Num a => a

c'PCI_EXP_DEVSTA_AUXPD :: Num a => a

c'PCI_EXP_DEVSTA_TRPND :: Num a => a

c'PCI_EXP_LNKCAP :: Num a => a

c'PCI_EXP_LNKCAP_SPEED :: Num a => a

c'PCI_EXP_LNKCAP_WIDTH :: Num a => a

c'PCI_EXP_LNKCAP_ASPM :: Num a => a

c'PCI_EXP_LNKCAP_L0S :: Num a => a

c'PCI_EXP_LNKCAP_L1 :: Num a => a

c'PCI_EXP_LNKCAP_CLOCKPM :: Num a => a

c'PCI_EXP_LNKCAP_SURPRISE :: Num a => a

c'PCI_EXP_LNKCAP_DLLA :: Num a => a

c'PCI_EXP_LNKCAP_LBNC :: Num a => a

c'PCI_EXP_LNKCAP_AOC :: Num a => a

c'PCI_EXP_LNKCAP_PORT :: Num a => a

c'PCI_EXP_LNKCTL :: Num a => a

c'PCI_EXP_LNKCTL_ASPM :: Num a => a

c'PCI_EXP_LNKCTL_RCB :: Num a => a

c'PCI_EXP_LNKCTL_DISABLE :: Num a => a

c'PCI_EXP_LNKCTL_RETRAIN :: Num a => a

c'PCI_EXP_LNKCTL_CLOCK :: Num a => a

c'PCI_EXP_LNKCTL_XSYNCH :: Num a => a

c'PCI_EXP_LNKCTL_CLOCKPM :: Num a => a

c'PCI_EXP_LNKCTL_HWAUTWD :: Num a => a

c'PCI_EXP_LNKCTL_BWMIE :: Num a => a

c'PCI_EXP_LNKCTL_AUTBWIE :: Num a => a

c'PCI_EXP_LNKSTA :: Num a => a

c'PCI_EXP_LNKSTA_SPEED :: Num a => a

c'PCI_EXP_LNKSTA_WIDTH :: Num a => a

c'PCI_EXP_LNKSTA_TR_ERR :: Num a => a

c'PCI_EXP_LNKSTA_TRAIN :: Num a => a

c'PCI_EXP_LNKSTA_SL_CLK :: Num a => a

c'PCI_EXP_LNKSTA_DL_ACT :: Num a => a

c'PCI_EXP_LNKSTA_BWMGMT :: Num a => a

c'PCI_EXP_LNKSTA_AUTBW :: Num a => a

c'PCI_EXP_SLTCAP :: Num a => a

c'PCI_EXP_SLTCAP_ATNB :: Num a => a

c'PCI_EXP_SLTCAP_PWRC :: Num a => a

c'PCI_EXP_SLTCAP_MRL :: Num a => a

c'PCI_EXP_SLTCAP_ATNI :: Num a => a

c'PCI_EXP_SLTCAP_PWRI :: Num a => a

c'PCI_EXP_SLTCAP_HPS :: Num a => a

c'PCI_EXP_SLTCAP_HPC :: Num a => a

c'PCI_EXP_SLTCAP_PWR_VAL :: Num a => a

c'PCI_EXP_SLTCAP_PWR_SCL :: Num a => a

c'PCI_EXP_SLTCAP_INTERLOCK :: Num a => a

c'PCI_EXP_SLTCAP_NOCMDCOMP :: Num a => a

c'PCI_EXP_SLTCAP_PSN :: Num a => a

c'PCI_EXP_SLTCTL :: Num a => a

c'PCI_EXP_SLTCTL_ATNB :: Num a => a

c'PCI_EXP_SLTCTL_PWRF :: Num a => a

c'PCI_EXP_SLTCTL_MRLS :: Num a => a

c'PCI_EXP_SLTCTL_PRSD :: Num a => a

c'PCI_EXP_SLTCTL_CMDC :: Num a => a

c'PCI_EXP_SLTCTL_HPIE :: Num a => a

c'PCI_EXP_SLTCTL_ATNI :: Num a => a

c'PCI_EXP_SLTCTL_PWRI :: Num a => a

c'PCI_EXP_SLTCTL_PWRC :: Num a => a

c'PCI_EXP_SLTCTL_INTERLOCK :: Num a => a

c'PCI_EXP_SLTCTL_LLCHG :: Num a => a

c'PCI_EXP_SLTSTA :: Num a => a

c'PCI_EXP_SLTSTA_ATNB :: Num a => a

c'PCI_EXP_SLTSTA_PWRF :: Num a => a

c'PCI_EXP_SLTSTA_MRLS :: Num a => a

c'PCI_EXP_SLTSTA_PRSD :: Num a => a

c'PCI_EXP_SLTSTA_CMDC :: Num a => a

c'PCI_EXP_SLTSTA_MRL_ST :: Num a => a

c'PCI_EXP_SLTSTA_PRES :: Num a => a

c'PCI_EXP_SLTSTA_INTERLOCK :: Num a => a

c'PCI_EXP_SLTSTA_LLCHG :: Num a => a

c'PCI_EXP_RTCTL :: Num a => a

c'PCI_EXP_RTCTL_SECEE :: Num a => a

c'PCI_EXP_RTCTL_SENFEE :: Num a => a

c'PCI_EXP_RTCTL_SEFEE :: Num a => a

c'PCI_EXP_RTCTL_PMEIE :: Num a => a

c'PCI_EXP_RTCTL_CRSVIS :: Num a => a

c'PCI_EXP_RTCAP :: Num a => a

c'PCI_EXP_RTCAP_CRSVIS :: Num a => a

c'PCI_EXP_RTSTA :: Num a => a

c'PCI_EXP_RTSTA_PME_REQID :: Num a => a

c'PCI_EXP_RTSTA_PME_STATUS :: Num a => a

c'PCI_EXP_RTSTA_PME_PENDING :: Num a => a

c'PCI_EXP_DEVCAP2 :: Num a => a

c'PCI_EXP_DEVCAP2_LTR :: Num a => a

c'PCI_EXP_DEVCAP2_OBFF :: CUInt -> CUInt

c'PCI_EXP_DEVCTL2 :: Num a => a

c'PCI_EXP_DEV2_TIMEOUT_RANGE :: CUInt -> CUInt

c'PCI_EXP_DEV2_TIMEOUT_VALUE :: CUShort -> CUShort

c'PCI_EXP_DEV2_TIMEOUT_DIS :: Num a => a

c'PCI_EXP_DEV2_ARI :: Num a => a

c'PCI_EXP_DEV2_LTR :: Num a => a

c'PCI_EXP_DEV2_OBFF :: CUShort -> CUShort

c'PCI_EXP_DEVSTA2 :: Num a => a

c'PCI_EXP_LNKCAP2 :: Num a => a

c'PCI_EXP_LNKCTL2 :: Num a => a

c'PCI_EXP_LNKCTL2_SPEED :: CUShort -> CUShort

c'PCI_EXP_LNKCTL2_CMPLNC :: Num a => a

c'PCI_EXP_LNKCTL2_SPEED_DIS :: Num a => a

c'PCI_EXP_LNKCTL2_DEEMPHASIS :: CUShort -> CUShort

c'PCI_EXP_LNKCTL2_MARGIN :: CUShort -> CUShort

c'PCI_EXP_LNKCTL2_MOD_CMPLNC :: Num a => a

c'PCI_EXP_LNKCTL2_CMPLNC_SOS :: Num a => a

c'PCI_EXP_LNKCTL2_COM_DEEMPHASIS :: CUShort -> CUShort

c'PCI_EXP_LNKSTA2 :: Num a => a

c'PCI_EXP_LINKSTA2_DEEMPHASIS :: CUShort -> CUShort

c'PCI_EXP_LINKSTA2_EQU_COMP :: Num a => a

c'PCI_EXP_LINKSTA2_EQU_PHASE1 :: Num a => a

c'PCI_EXP_LINKSTA2_EQU_PHASE2 :: Num a => a

c'PCI_EXP_LINKSTA2_EQU_PHASE3 :: Num a => a

c'PCI_EXP_LINKSTA2_EQU_REQ :: Num a => a

c'PCI_EXP_SLTCAP2 :: Num a => a

c'PCI_EXP_SLTCTL2 :: Num a => a

c'PCI_EXP_SLTSTA2 :: Num a => a

c'PCI_MSIX_ENABLE :: Num a => a

c'PCI_MSIX_MASK :: Num a => a

c'PCI_MSIX_TABSIZE :: Num a => a

c'PCI_MSIX_TABLE :: Num a => a

c'PCI_MSIX_PBA :: Num a => a

c'PCI_MSIX_BIR :: Num a => a

c'PCI_SSVID_VENDOR :: Num a => a

c'PCI_SSVID_DEVICE :: Num a => a

c'PCI_AF_CAP :: Num a => a

c'PCI_AF_CAP_TP :: Num a => a

c'PCI_AF_CAP_FLR :: Num a => a

c'PCI_AF_CTRL :: Num a => a

c'PCI_AF_CTRL_FLR :: Num a => a

c'PCI_AF_STATUS :: Num a => a

c'PCI_AF_STATUS_TP :: Num a => a

c'PCI_SATA_HBA_BARS :: Num a => a

c'PCI_SATA_HBA_REG0 :: Num a => a

c'PCI_EA_CAP_TYPE1_SECONDARY :: Num a => a

c'PCI_EA_CAP_TYPE1_SUBORDINATE :: Num a => a

c'PCI_EA_CAP_ENT_WRITABLE :: Num a => a

c'PCI_EA_CAP_ENT_ENABLE :: Num a => a

c'PCI_ERR_UNCOR_STATUS :: Num a => a

c'PCI_ERR_UNC_TRAIN :: Num a => a

c'PCI_ERR_UNC_DLP :: Num a => a

c'PCI_ERR_UNC_SDES :: Num a => a

c'PCI_ERR_UNC_POISON_TLP :: Num a => a

c'PCI_ERR_UNC_FCP :: Num a => a

c'PCI_ERR_UNC_COMP_TIME :: Num a => a

c'PCI_ERR_UNC_COMP_ABORT :: Num a => a

c'PCI_ERR_UNC_UNX_COMP :: Num a => a

c'PCI_ERR_UNC_RX_OVER :: Num a => a

c'PCI_ERR_UNC_MALF_TLP :: Num a => a

c'PCI_ERR_UNC_ECRC :: Num a => a

c'PCI_ERR_UNC_UNSUP :: Num a => a

c'PCI_ERR_UNC_ACS_VIOL :: Num a => a

c'PCI_ERR_UNCOR_MASK :: Num a => a

c'PCI_ERR_UNCOR_SEVER :: Num a => a

c'PCI_ERR_COR_STATUS :: Num a => a

c'PCI_ERR_COR_RCVR :: Num a => a

c'PCI_ERR_COR_BAD_TLP :: Num a => a

c'PCI_ERR_COR_BAD_DLLP :: Num a => a

c'PCI_ERR_COR_REP_ROLL :: Num a => a

c'PCI_ERR_COR_REP_TIMER :: Num a => a

c'PCI_ERR_COR_REP_ANFE :: Num a => a

c'PCI_ERR_COR_MASK :: Num a => a

c'PCI_ERR_CAP :: Num a => a

c'PCI_ERR_CAP_FEP :: CUInt -> CUInt

c'PCI_ERR_CAP_ECRC_GENC :: Num a => a

c'PCI_ERR_CAP_ECRC_GENE :: Num a => a

c'PCI_ERR_CAP_ECRC_CHKC :: Num a => a

c'PCI_ERR_CAP_ECRC_CHKE :: Num a => a

c'PCI_ERR_HEADER_LOG :: Num a => a

c'PCI_ERR_ROOT_COMMAND :: Num a => a

c'PCI_ERR_ROOT_STATUS :: Num a => a

c'PCI_ERR_ROOT_COR_SRC :: Num a => a

c'PCI_ERR_ROOT_SRC :: Num a => a

c'PCI_VC_PORT_REG1 :: Num a => a

c'PCI_VC_PORT_REG2 :: Num a => a

c'PCI_VC_PORT_CTRL :: Num a => a

c'PCI_VC_PORT_STATUS :: Num a => a

c'PCI_VC_RES_CAP :: Num a => a

c'PCI_VC_RES_CTRL :: Num a => a

c'PCI_VC_RES_STATUS :: Num a => a

c'PCI_PWR_DSR :: Num a => a

c'PCI_PWR_DATA :: Num a => a

c'PCI_PWR_DATA_BASE :: CUInt -> CUInt

c'PCI_PWR_DATA_SCALE :: CUInt -> CUInt

c'PCI_PWR_DATA_PM_SUB :: CUInt -> CUInt

c'PCI_PWR_DATA_PM_STATE :: CUInt -> CUInt

c'PCI_PWR_DATA_TYPE :: CUInt -> CUInt

c'PCI_PWR_DATA_RAIL :: CUInt -> CUInt

c'PCI_PWR_CAP :: Num a => a

c'PCI_PWR_CAP_BUDGET :: CUInt -> CUInt

c'PCI_RCLINK_ESD :: Num a => a

c'PCI_RCLINK_LINK1 :: Num a => a

c'PCI_RCLINK_LINK_DESC :: Num a => a

c'PCI_RCLINK_LINK_ADDR :: Num a => a

c'PCI_RCLINK_LINK_SIZE :: Num a => a

c'PCI_EVNDR_HEADER :: Num a => a

c'PCI_EVNDR_REGISTERS :: Num a => a

c'PCI_ACS_CAP :: Num a => a

c'PCI_ACS_CAP_VALID :: Num a => a

c'PCI_ACS_CAP_BLOCK :: Num a => a

c'PCI_ACS_CAP_REQ_RED :: Num a => a

c'PCI_ACS_CAP_CMPLT_RED :: Num a => a

c'PCI_ACS_CAP_FORWARD :: Num a => a

c'PCI_ACS_CAP_EGRESS :: Num a => a

c'PCI_ACS_CAP_TRANS :: Num a => a

c'PCI_ACS_CAP_VECTOR :: CUInt -> CUInt

c'PCI_ACS_CTRL :: Num a => a

c'PCI_ACS_CTRL_VALID :: Num a => a

c'PCI_ACS_CTRL_BLOCK :: Num a => a

c'PCI_ACS_CTRL_REQ_RED :: Num a => a

c'PCI_ACS_CTRL_CMPLT_RED :: Num a => a

c'PCI_ACS_CTRL_FORWARD :: Num a => a

c'PCI_ACS_CTRL_EGRESS :: Num a => a

c'PCI_ACS_CTRL_TRANS :: Num a => a

c'PCI_ACS_EGRESS_CTRL :: Num a => a

c'PCI_ARI_CAP :: Num a => a

c'PCI_ARI_CAP_MFVC :: Num a => a

c'PCI_ARI_CAP_ACS :: Num a => a

c'PCI_ARI_CAP_NFN :: CUShort -> CUShort

c'PCI_ARI_CTRL :: Num a => a

c'PCI_ARI_CTRL_MFVC :: Num a => a

c'PCI_ARI_CTRL_ACS :: Num a => a

c'PCI_ARI_CTRL_FG :: CUShort -> CUShort

c'PCI_ATS_CAP :: Num a => a

c'PCI_ATS_CAP_IQD :: CUShort -> CUShort

c'PCI_ATS_CTRL :: Num a => a

c'PCI_ATS_CTRL_STU :: CUShort -> CUShort

c'PCI_ATS_CTRL_ENABLE :: Num a => a

c'PCI_IOV_CAP :: Num a => a

c'PCI_IOV_CAP_VFM :: Num a => a

c'PCI_IOV_CAP_IMN :: CUInt -> CUInt

c'PCI_IOV_CTRL :: Num a => a

c'PCI_IOV_CTRL_VFE :: Num a => a

c'PCI_IOV_CTRL_VFME :: Num a => a

c'PCI_IOV_CTRL_VFMIE :: Num a => a

c'PCI_IOV_CTRL_MSE :: Num a => a

c'PCI_IOV_CTRL_ARI :: Num a => a

c'PCI_IOV_STATUS :: Num a => a

c'PCI_IOV_STATUS_MS :: Num a => a

c'PCI_IOV_INITIALVF :: Num a => a

c'PCI_IOV_TOTALVF :: Num a => a

c'PCI_IOV_NUMVF :: Num a => a

c'PCI_IOV_FDL :: Num a => a

c'PCI_IOV_OFFSET :: Num a => a

c'PCI_IOV_STRIDE :: Num a => a

c'PCI_IOV_DID :: Num a => a

c'PCI_IOV_SUPPS :: Num a => a

c'PCI_IOV_SYSPS :: Num a => a

c'PCI_IOV_BAR_BASE :: Num a => a

c'PCI_IOV_NUM_BAR :: Num a => a

c'PCI_IOV_MSAO :: Num a => a

c'PCI_IOV_MSA_BIR :: CUInt -> CUInt

c'PCI_IOV_MSA_OFFSET :: CUInt -> CUInt

c'PCI_PRI_CTRL :: Num a => a

Page Request Interface

c'PCI_PRI_CTRL_ENABLE :: Num a => a

c'PCI_PRI_CTRL_RESET :: Num a => a

c'PCI_PRI_STATUS :: Num a => a

c'PCI_PRI_STATUS_RF :: Num a => a

c'PCI_PRI_STATUS_UPRGI :: Num a => a

c'PCI_PRI_STATUS_STOPPED :: Num a => a

c'PCI_PRI_MAX_REQ :: Num a => a

c'PCI_PRI_ALLOC_REQ :: Num a => a

c'PCI_TPH_CAPABILITIES :: Num a => a

c'PCI_TPH_INTVEC_SUP :: Num a => a

c'PCI_TPH_DEV_SUP :: Num a => a

c'PCI_TPH_EXT_REQ_SUP :: Num a => a

c'PCI_TPH_ST_LOC_MASK :: Num a => a

c'PCI_TPH_ST_NONE :: Num a => a

c'PCI_TPH_ST_CAP :: Num a => a

c'PCI_TPH_ST_MSIX :: Num a => a

c'PCI_TPH_ST_SIZE_SHIFT :: Num a => a

c'PCI_LTR_MAX_SNOOP :: Num a => a

c'PCI_LTR_VALUE_MASK :: Num a => a

c'PCI_LTR_SCALE_SHIFT :: Num a => a

c'PCI_LTR_SCALE_MASK :: Num a => a

c'PCI_LTR_MAX_NOSNOOP :: Num a => a

c'PCI_PASID_CAP :: Num a => a

Process Address Space ID

0x04 PASID feature register

c'PCI_PASID_CAP_EXEC :: Num a => a

0x02 Exec permissions Supported

c'PCI_PASID_CAP_PRIV :: Num a => a

c'PCI_PASID_CAP_WIDTH :: CUShort -> CUShort

c'PCI_PASID_CTRL :: Num a => a

c'PCI_PASID_CTRL_ENABLE :: Num a => a

c'PCI_PASID_CTRL_EXEC :: Num a => a

c'PCI_PASID_CTRL_PRIV :: Num a => a

c'PCI_DPC_CAP :: Num a => a

c'PCI_DPC_CAP_INT_MSG :: CUInt -> CUInt

c'PCI_DPC_CAP_RP_EXT :: Num a => a

c'PCI_DPC_CAP_TLP_BLOCK :: Num a => a

c'PCI_DPC_CAP_SW_TRIGGER :: Num a => a

c'PCI_DPC_CAP_RP_LOG :: CUInt -> CUInt

c'PCI_DPC_CAP_DL_ACT_ERR :: Num a => a

c'PCI_DPC_CTL :: Num a => a

c'PCI_DPC_CTL_TRIGGER :: CUInt -> CUInt

c'PCI_DPC_CTL_CMPL :: Num a => a

c'PCI_DPC_CTL_INT :: Num a => a

c'PCI_DPC_CTL_ERR_COR :: Num a => a

c'PCI_DPC_CTL_TLP :: Num a => a

c'PCI_DPC_CTL_SW_TRIGGER :: Num a => a

c'PCI_DPC_CTL_DL_ACTIVE :: Num a => a

c'PCI_DPC_STATUS :: Num a => a

c'PCI_DPC_STS_TRIGGER :: Num a => a

c'PCI_DPC_STS_REASON :: CUInt -> CUInt

c'PCI_DPC_STS_INT :: Num a => a

c'PCI_DPC_STS_RP_BUSY :: Num a => a

c'PCI_DPC_STS_TRIGGER_EXT :: CUInt -> CUInt

c'PCI_DPC_STS_PIO_FEP :: CUInt -> CUInt

c'PCI_DPC_SOURCE :: Num a => a

c'PCI_L1PM_SUBSTAT_CAP :: Num a => a

c'PCI_L1PM_SUBSTAT_CAP_PM_L12 :: Num a => a

c'PCI_L1PM_SUBSTAT_CAP_PM_L11 :: Num a => a

c'PCI_L1PM_SUBSTAT_CAP_ASPM_L12 :: Num a => a

c'PCI_L1PM_SUBSTAT_CAP_ASPM_L11 :: Num a => a

c'PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP :: Num a => a

c'PCI_L1PM_SUBSTAT_CTL1 :: Num a => a

c'PCI_L1PM_SUBSTAT_CTL1_PM_L12 :: Num a => a

c'PCI_L1PM_SUBSTAT_CTL1_PM_L11 :: Num a => a

c'PCI_L1PM_SUBSTAT_CTL1_ASPM_L12 :: Num a => a

c'PCI_L1PM_SUBSTAT_CTL1_ASPM_L11 :: Num a => a

c'PCI_L1PM_SUBSTAT_CTL2 :: Num a => a

c'PCI_DEVFN :: CUChar -> CUChar -> CUChar

c'PCI_SLOT :: CUChar -> CUChar

c'PCI_FUNC :: CUChar -> CUChar

c'PCI_CLASS_NOT_DEFINED :: Num a => a

c'PCI_CLASS_NOT_DEFINED_VGA :: Num a => a

c'PCI_BASE_CLASS_STORAGE :: Num a => a

c'PCI_CLASS_STORAGE_SCSI :: Num a => a

c'PCI_CLASS_STORAGE_IDE :: Num a => a

c'PCI_CLASS_STORAGE_FLOPPY :: Num a => a

c'PCI_CLASS_STORAGE_IPI :: Num a => a

c'PCI_CLASS_STORAGE_RAID :: Num a => a

c'PCI_CLASS_STORAGE_ATA :: Num a => a

c'PCI_CLASS_STORAGE_SATA :: Num a => a

c'PCI_CLASS_STORAGE_SAS :: Num a => a

c'PCI_CLASS_STORAGE_OTHER :: Num a => a

c'PCI_BASE_CLASS_NETWORK :: Num a => a

c'PCI_CLASS_NETWORK_ETHERNET :: Num a => a

c'PCI_CLASS_NETWORK_TOKEN_RING :: Num a => a

c'PCI_CLASS_NETWORK_FDDI :: Num a => a

c'PCI_CLASS_NETWORK_ATM :: Num a => a

c'PCI_CLASS_NETWORK_ISDN :: Num a => a

c'PCI_CLASS_NETWORK_OTHER :: Num a => a

c'PCI_BASE_CLASS_DISPLAY :: Num a => a

c'PCI_CLASS_DISPLAY_VGA :: Num a => a

c'PCI_CLASS_DISPLAY_XGA :: Num a => a

c'PCI_CLASS_DISPLAY_3D :: Num a => a

c'PCI_CLASS_DISPLAY_OTHER :: Num a => a

c'PCI_BASE_CLASS_MULTIMEDIA :: Num a => a

c'PCI_CLASS_MULTIMEDIA_VIDEO :: Num a => a

c'PCI_CLASS_MULTIMEDIA_AUDIO :: Num a => a

c'PCI_CLASS_MULTIMEDIA_PHONE :: Num a => a

c'PCI_CLASS_MULTIMEDIA_AUDIO_DEV :: Num a => a

c'PCI_CLASS_MULTIMEDIA_OTHER :: Num a => a

c'PCI_BASE_CLASS_MEMORY :: Num a => a

c'PCI_CLASS_MEMORY_RAM :: Num a => a

c'PCI_CLASS_MEMORY_FLASH :: Num a => a

c'PCI_CLASS_MEMORY_OTHER :: Num a => a

c'PCI_BASE_CLASS_BRIDGE :: Num a => a

c'PCI_CLASS_BRIDGE_HOST :: Num a => a

c'PCI_CLASS_BRIDGE_ISA :: Num a => a

c'PCI_CLASS_BRIDGE_EISA :: Num a => a

c'PCI_CLASS_BRIDGE_MC :: Num a => a

c'PCI_CLASS_BRIDGE_PCI :: Num a => a

c'PCI_CLASS_BRIDGE_PCMCIA :: Num a => a

c'PCI_CLASS_BRIDGE_NUBUS :: Num a => a

c'PCI_CLASS_BRIDGE_CARDBUS :: Num a => a

c'PCI_CLASS_BRIDGE_RACEWAY :: Num a => a

c'PCI_CLASS_BRIDGE_PCI_SEMI :: Num a => a

c'PCI_CLASS_BRIDGE_IB_TO_PCI :: Num a => a

c'PCI_CLASS_BRIDGE_OTHER :: Num a => a

c'PCI_BASE_CLASS_COMMUNICATION :: Num a => a

c'PCI_CLASS_COMMUNICATION_SERIAL :: Num a => a

c'PCI_CLASS_COMMUNICATION_PARALLEL :: Num a => a

c'PCI_CLASS_COMMUNICATION_MSERIAL :: Num a => a

c'PCI_CLASS_COMMUNICATION_MODEM :: Num a => a

c'PCI_CLASS_COMMUNICATION_OTHER :: Num a => a

c'PCI_BASE_CLASS_SYSTEM :: Num a => a

c'PCI_CLASS_SYSTEM_PIC :: Num a => a

c'PCI_CLASS_SYSTEM_DMA :: Num a => a

c'PCI_CLASS_SYSTEM_TIMER :: Num a => a

c'PCI_CLASS_SYSTEM_RTC :: Num a => a

c'PCI_CLASS_SYSTEM_PCI_HOTPLUG :: Num a => a

c'PCI_CLASS_SYSTEM_OTHER :: Num a => a

c'PCI_BASE_CLASS_INPUT :: Num a => a

c'PCI_CLASS_INPUT_KEYBOARD :: Num a => a

c'PCI_CLASS_INPUT_PEN :: Num a => a

c'PCI_CLASS_INPUT_MOUSE :: Num a => a

c'PCI_CLASS_INPUT_SCANNER :: Num a => a

c'PCI_CLASS_INPUT_GAMEPORT :: Num a => a

c'PCI_CLASS_INPUT_OTHER :: Num a => a

c'PCI_BASE_CLASS_DOCKING :: Num a => a

c'PCI_CLASS_DOCKING_GENERIC :: Num a => a

c'PCI_CLASS_DOCKING_OTHER :: Num a => a

c'PCI_BASE_CLASS_PROCESSOR :: Num a => a

c'PCI_CLASS_PROCESSOR_386 :: Num a => a

c'PCI_CLASS_PROCESSOR_486 :: Num a => a

c'PCI_CLASS_PROCESSOR_PENTIUM :: Num a => a

c'PCI_CLASS_PROCESSOR_ALPHA :: Num a => a

c'PCI_CLASS_PROCESSOR_POWERPC :: Num a => a

c'PCI_CLASS_PROCESSOR_MIPS :: Num a => a

c'PCI_CLASS_PROCESSOR_CO :: Num a => a

c'PCI_BASE_CLASS_SERIAL :: Num a => a

c'PCI_CLASS_SERIAL_FIREWIRE :: Num a => a

c'PCI_CLASS_SERIAL_ACCESS :: Num a => a

c'PCI_CLASS_SERIAL_SSA :: Num a => a

c'PCI_CLASS_SERIAL_USB :: Num a => a

c'PCI_CLASS_SERIAL_FIBER :: Num a => a

c'PCI_CLASS_SERIAL_SMBUS :: Num a => a

c'PCI_CLASS_SERIAL_INFINIBAND :: Num a => a

c'PCI_BASE_CLASS_WIRELESS :: Num a => a

c'PCI_CLASS_WIRELESS_IRDA :: Num a => a

c'PCI_CLASS_WIRELESS_CONSUMER_IR :: Num a => a

c'PCI_CLASS_WIRELESS_RF :: Num a => a

c'PCI_CLASS_WIRELESS_OTHER :: Num a => a

c'PCI_BASE_CLASS_INTELLIGENT :: Num a => a

c'PCI_CLASS_INTELLIGENT_I2O :: Num a => a

c'PCI_BASE_CLASS_SATELLITE :: Num a => a

c'PCI_CLASS_SATELLITE_TV :: Num a => a

c'PCI_CLASS_SATELLITE_AUDIO :: Num a => a

c'PCI_CLASS_SATELLITE_VOICE :: Num a => a

c'PCI_CLASS_SATELLITE_DATA :: Num a => a

c'PCI_BASE_CLASS_CRYPT :: Num a => a

c'PCI_CLASS_CRYPT_NETWORK :: Num a => a

c'PCI_CLASS_CRYPT_ENTERTAINMENT :: Num a => a

c'PCI_CLASS_CRYPT_OTHER :: Num a => a

c'PCI_BASE_CLASS_SIGNAL :: Num a => a

c'PCI_CLASS_SIGNAL_DPIO :: Num a => a

c'PCI_CLASS_SIGNAL_PERF_CTR :: Num a => a

c'PCI_CLASS_SIGNAL_SYNCHRONIZER :: Num a => a

c'PCI_CLASS_SIGNAL_OTHER :: Num a => a

c'PCI_CLASS_OTHERS :: Num a => a

c'PCI_VENDOR_ID_INTEL :: Num a => a

c'PCI_VENDOR_ID_COMPAQ :: Num a => a

c'PCI_IORESOURCE_PCI_EA_BEI :: Num a => a