h$F       !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~None! &(-/35678:<>?'circusMaster list of cells, and their associated names is available here: https://raw.githubusercontent.com/nturley/netlistsvg/master/lib/default.svg?sanitize=truecircus How many bits wide is the given ?circus Is the given  signed? circus)The symbol to use when drawing this cell. circus#Which ports are inputs and outputs.circusWhat are the ports connected to? Each port may connect to several bits, but make sure you set the  cell  if this is the case.circusA single wire. Bits are defined implicitly by a unique ID. Every component that references the bit will be connected with a common node.circus*Whether this port is an input or an outputcircusThe individual wires connected to this port. They are numbered in the same order they are described here.!circusInputs and outputs"circus Components#circusA collection of modules.circus!Helper function for constructing s.circus!Helper function for constructing s with explicit attributes.circus Attributes;   "!#$%&'()*+,-./0123456;#$% "!  6543210/.-,+*)('&None&(-/35678:<>?LcircusRecursively delete cells that output only bits which are unused in the circuit.None&(-/35678:<>? circusSynthesize a fresh , suitable for connecting  s together.circusAdd a  to the  under construction.circusLike , but works in pure contexts.circusGiven a mapping from source  s to target 5s, replace all occurences of the source bits in the  with the target bits.!This function allows you to call  as you go, and create feedback loops later without needing to know about them in advance.None&(-/35678:<>?        !!"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~%circus-0.1.0.0-7gwvoNsbnBR3ebwlAtgx3C Circus.TypesCircus.Simplify Circus.DSL Paths_circusCellType CellGeneric DirectionInputOutput ParameterWidthSignedCellcellTypecellParameterscellAttributescellPortDirectionscellConnectionsBitgetBitPort portDirectionportBitsCellName getCellNamePortName getPortName ModuleName getModuleNameModule modulePorts moduleCellsSchema schemaModules CellConstantCellGeCellLtCellDffnCellDffCellEqCellAddCellNotCellXnorCellXorCellNorCellNandCellOrCellAnd CellTribuf CellMuxBusCellMux$fFromJSONKeyParameter$fToJSONKeyParameter$fFromJSONDirection$fToJSONDirection$fFromJSONCellType$fToJSONCellType$fMonoidModule$fSemigroupModule $fEqSchema $fShowSchema $fDataSchema$fSemigroupSchema$fMonoidSchema $fEqModule $fShowModule $fDataModule$fEqCell $fShowCell $fDataCell $fEqCellType $fOrdCellType$fShowCellType$fDataCellType$fEqPort $fShowPort $fDataPort $fEqDirection$fOrdDirection$fShowDirection$fReadDirection$fEnumDirection$fBoundedDirection$fDataDirection $fEqParameter$fOrdParameter$fShowParameter$fGenericParameter$fDataParameter$fFromJSONParameter$fToJSONParameter$fEqBit$fOrdBit $fShowBit $fDataBit$fNumBit $fToJSONBit $fFromJSONBit$fDataCellName $fEqCellName $fOrdCellName$fShowCellName$fIsStringCellName$fToJSONKeyCellName$fFromJSONKeyCellName$fFromJSONCellName$fToJSONCellName$fDataPortName $fEqPortName $fOrdPortName$fShowPortName$fIsStringPortName$fToJSONKeyPortName$fFromJSONKeyPortName$fFromJSONPortName$fToJSONPortName$fDataModuleName$fEqModuleName$fOrdModuleName$fShowModuleName$fIsStringModuleName$fToJSONKeyModuleName$fFromJSONKeyModuleName$fFromJSONModuleName$fToJSONModuleName$fFromJSONCell $fToJSONCell$fFromJSONPort $fToJSONPort$fFromJSONModule$fToJSONModulerenderModuleBSrenderModuleStringmkCellmkCell'$fFromJSONSchema$fToJSONSchemasimplify GraphState gs_next_port gs_modulefreshBitaddCell unifyBitsPure unifyBits$fMonoidGraphState$fSemigroupGraphState$fGenericGraphStateversion getBinDir getLibDir getDynLibDir getDataDir getLibexecDir getSysconfDirgetDataFileName