module CLasH.VHDL where
import qualified Data.Map as Map
import qualified Maybe
import qualified Control.Arrow as Arrow
import Data.Accessor
import qualified Data.Accessor.Monad.Trans.State as MonadState
import qualified Language.VHDL.AST as AST
import qualified CoreSyn
import CLasH.Translator.TranslatorTypes
import CLasH.VHDL.VHDLTypes
import CLasH.VHDL.VHDLTools
import CLasH.VHDL.Constants
import CLasH.VHDL.Generate
createDesignFiles ::
[CoreSyn.CoreBndr]
-> TranslatorSession [(AST.VHDLId, AST.DesignFile)]
createDesignFiles topbndrs = do
bndrss <- mapM recurseArchitectures topbndrs
let bndrs = concat bndrss
lunits <- mapM createLibraryUnit bndrs
typepackage <- createTypesPackage
let files = map (Arrow.second $ AST.DesignFile full_context) lunits
return $ typepackage : files
where
full_context =
mkUseAll ["work", "types"]
: (mkUseAll ["work"]
: ieee_context)
ieee_context = [
AST.Library $ mkVHDLBasicId "IEEE",
mkUseAll ["IEEE", "std_logic_1164"],
mkUseAll ["IEEE", "numeric_std"],
mkUseAll ["std", "textio"]
]
recurseArchitectures ::
CoreSyn.CoreBndr
-> TranslatorSession [CoreSyn.CoreBndr]
recurseArchitectures bndr = do
(_, used) <- getArchitecture bndr
useds <- mapM recurseArchitectures used
return $ bndr : (concat useds)
createTypesPackage ::
TranslatorSession (AST.VHDLId, AST.DesignFile)
createTypesPackage = do
tyfuns <- MonadState.get (tsType .> tsTypeFuns)
let tyfun_decls = mkBuiltInShow ++ map snd (Map.elems tyfuns)
ty_decls_maybes <- MonadState.get (tsType .> tsTypeDecls)
let ty_decls = Maybe.catMaybes ty_decls_maybes
let subProgSpecs = map (\(AST.SubProgBody spec _ _) -> AST.PDISS spec) tyfun_decls
let type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ ty_decls ++ subProgSpecs)
let type_package_body = AST.LUPackageBody $ AST.PackageBody typesId tyfun_decls
return (mkVHDLBasicId "types", AST.DesignFile ieee_context [type_package_dec, type_package_body])
where
tfvec_index_decl = AST.PDISD $ AST.SubtypeDec tfvec_indexTM tfvec_index_def
tfvec_range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit "-1") (AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerTM) (AST.NSimple highId) Nothing)
tfvec_index_def = AST.SubtypeIn integerTM (Just tfvec_range)
mkUseAll :: [String] -> AST.ContextItem
mkUseAll ss =
AST.Use $ from AST.:.: AST.All
where
base_prefix = (AST.NSimple $ mkVHDLBasicId $ head ss)
from = foldl select base_prefix (tail ss)
select prefix s = AST.NSelected $ prefix AST.:.: (AST.SSimple $ mkVHDLBasicId s)
createLibraryUnit ::
CoreSyn.CoreBndr
-> TranslatorSession (AST.VHDLId, [AST.LibraryUnit])
createLibraryUnit bndr = do
entity <- getEntity bndr
(arch, _) <- getArchitecture bndr
return (ent_id entity, [AST.LUEntity (ent_dec entity), AST.LUArch arch])