Safe Haskell | None |
---|---|
Language | Haskell2010 |
Generate a VHDL testbench for a component given a set of stimuli and a set of matching expected outputs
- genTestBench :: DebugLevel -> Supply -> PrimMap -> (HashMap TyConName TyCon -> Type -> Maybe (Either String HWType)) -> HashMap TyConName TyCon -> (HashMap TyConName TyCon -> Term -> Term) -> VHDLState -> Int -> HashMap TmName (Type, Term) -> Maybe TmName -> Maybe TmName -> Component -> IO ([Component], VHDLState)
Documentation
:: DebugLevel | |
-> Supply | |
-> PrimMap | Primitives |
-> (HashMap TyConName TyCon -> Type -> Maybe (Either String HWType)) | |
-> HashMap TyConName TyCon | |
-> (HashMap TyConName TyCon -> Term -> Term) | |
-> VHDLState | |
-> Int | |
-> HashMap TmName (Type, Term) | Global binders |
-> Maybe TmName | Stimuli |
-> Maybe TmName | Expected output |
-> Component | Component to generate TB for |
-> IO ([Component], VHDLState) |
Generate a VHDL testbench for a component given a set of stimuli and a set of matching expected outputs