CLaSH.Driver.TestbenchGen

Generate a VHDL testbench for a component given a set of stimuli and a set of matching expected outputs

Documentation

genTestBench

Arguments

:: DebugLevel

-> Supply

-> PrimMap

Primitives

-> (HashMap TyConName TyCon -> Type -> Maybe (Either String HWType))

-> HashMap TyConName TyCon

-> (HashMap TyConName TyCon -> Term -> Term)

-> VHDLState

-> Int

-> HashMap TmName (Type, Term)

Global binders

-> Maybe TmName

Stimuli

-> Maybe TmName

Expected output

-> Component

Component to generate TB for

-> IO ([Component], VHDLState)

Generate a VHDL testbench for a component given a set of stimuli and a set of matching expected outputs