Copyright | (C) 2015, University of Twente |
---|---|
License | BSD2 (see the file LICENSE) |
Maintainer | Christiaan Baaij <christiaan.baaij@gmail.com> |
Safe Haskell | None |
Language | Haskell2010 |
Extensions |
|
- mkTopWrapper :: PrimMap -> Maybe TopEntity -> String -> Component -> Component
- extraIn :: Maybe TopEntity -> [(Identifier, HWType)]
- extraOut :: Maybe TopEntity -> [(Identifier, HWType)]
- mkInput :: [Identifier] -> (Identifier, HWType) -> Int -> ([Identifier], ([(Identifier, HWType)], ([Declaration], Identifier)))
- mkVectorChain :: Int -> HWType -> [Identifier] -> Expr
- mkOutput :: [Identifier] -> (Identifier, HWType) -> Int -> ([Identifier], ([(Identifier, HWType)], ([Declaration], Identifier)))
- mkClocks :: PrimMap -> [(Identifier, HWType)] -> Maybe TopEntity -> [Declaration]
- stringToVar :: String -> Expr
- mkClock :: ClockSource -> ([Declaration], (Identifier, [String], Bool))
- mkClockDecl :: String -> Declaration
- clockPorts :: Maybe (String, String) -> [(String, String)] -> ([(Identifier, Expr)], [String])
- mkResets :: PrimMap -> [(Identifier, HWType)] -> [(Identifier, [String], Bool)] -> [Declaration]
- genSyncReset :: PrimMap -> Identifier -> Identifier -> Text -> Int -> NetlistMonad [Declaration]
- unsafeRunNetlist :: NetlistMonad a -> a
Documentation
:: PrimMap | |
-> Maybe TopEntity | TopEntity specifications |
-> String | Name of the module containing the |
-> Component | Entity to wrap |
-> Component |
Create a wrapper around a component, potentially initiating clock sources
extraOut :: Maybe TopEntity -> [(Identifier, HWType)] Source
Create extra output ports for the wrapper
mkInput :: [Identifier] -> (Identifier, HWType) -> Int -> ([Identifier], ([(Identifier, HWType)], ([Declaration], Identifier))) Source
Generate input port mappings
mkVectorChain :: Int -> HWType -> [Identifier] -> Expr Source
Create a Vector chain for a list of Identifier
s
mkOutput :: [Identifier] -> (Identifier, HWType) -> Int -> ([Identifier], ([(Identifier, HWType)], ([Declaration], Identifier))) Source
Generate output port mappings
mkClocks :: PrimMap -> [(Identifier, HWType)] -> Maybe TopEntity -> [Declaration] Source
Create clock generators
stringToVar :: String -> Expr Source
mkClock :: ClockSource -> ([Declaration], (Identifier, [String], Bool)) Source
Create a single clock generator
mkClockDecl :: String -> Declaration Source
clockPorts :: Maybe (String, String) -> [(String, String)] -> ([(Identifier, Expr)], [String]) Source
Create a single clock path
mkResets :: PrimMap -> [(Identifier, HWType)] -> [(Identifier, [String], Bool)] -> [Declaration] Source
Generate resets
genSyncReset :: PrimMap -> Identifier -> Identifier -> Text -> Int -> NetlistMonad [Declaration] Source
Generate a reset synchroniser that synchronously de-asserts an asynchronous reset signal
unsafeRunNetlist :: NetlistMonad a -> a Source
The NetListMonad
is an transformer stack with IO
at the bottom.
So we must use unsafePerformIO
.