clash-lib: CAES Language for Synchronous Hardware - As a Library

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CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

This package provides:

  • The CoreHW internal language: SystemF + Letrec + Case-decomposition

  • The normalisation process that brings CoreHW in a normal form that can be converted to a netlist

  • Blackbox/Primitive Handling

Front-ends (for: parsing, typecheck, etc.) are provided by separate packages:

Prelude library: http://hackage.haskell.org/package/clash-prelude


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Change log CHANGELOG.md
Dependencies aeson (>=0.6.2.0 && <0.12), attoparsec (>=0.10.4.0 && <0.14), base (>=4.8 && <5), bytestring (>=0.10.0.2 && <0.11), clash-prelude (>=0.10.4 && <0.11), concurrent-supply (>=0.1.7 && <0.2), containers (>=0.5.0.0 && <0.6), deepseq (>=1.3.0.2 && <1.5), directory (>=1.2.0.1 && <1.3), errors (>=1.4.2 && <2.2), fgl (>=5.4.2.4 && <5.6), filepath (>=1.3.0.1 && <1.5), ghc (>=7.10.1 && <8.1), hashable (>=1.2.1.0 && <1.3), integer-gmp (>=1.0 && <1.1), lens (>=3.9.2 && <4.15), mtl (>=2.1.2 && <2.3), pretty (>=1.1.1.0 && <1.2), process (>=1.1.0.2 && <1.5), template-haskell (>=2.8.0.0 && <2.12), text (>=0.11.3.1 && <1.3), time (>=1.4.0.1 && <1.7), transformers (>=0.3.0.0 && <0.6), unbound-generics (>=0.1 && <0.4), unordered-containers (>=0.2.3.3 && <0.3), uu-parsinglib (>=2.8.1 && <2.10), wl-pprint-text (>=1.1.0.0 && <1.2) [details]
License BSD-2-Clause
Copyright Copyright © 2012-2016 University of Twente
Author Christiaan Baaij
Maintainer Christiaan Baaij <christiaan.baaij@gmail.com>
Category Hardware
Home page http://www.clash-lang.org/
Bug tracker http://github.com/clash-lang/clash-compiler/issues
Source repo head: git clone https://github.com/clash-lang/clash-compiler.git
Uploaded by ChristiaanBaaij at 2016-07-19T13:19:24Z
Distributions Arch:1.8.1, NixOS:1.8.1, Stackage:1.8.1
Reverse Dependencies 10 direct, 0 indirect [details]
Downloads 59756 total (139 in the last 30 days)
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Readme for clash-lib-0.6.19

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clash-lib - CλaSH compiler, as a library

  • See the LICENSE file for license and copyright details

CλaSH - A functional hardware description language

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum