clash-prelude-0.11.2: CAES Language for Synchronous Hardware - Prelude library

Copyright(C) 2015-2016 University of Twente
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <christiaan.baaij@gmail.com>
Safe HaskellTrustworthy
LanguageHaskell2010
Extensions
  • Cpp
  • MonoLocalBinds
  • ScopedTypeVariables
  • BangPatterns
  • TypeFamilies
  • DataKinds
  • FlexibleContexts
  • MagicHash
  • KindSignatures
  • TypeOperators
  • ExplicitNamespaces
  • ExplicitForAll
  • TypeApplications

CLaSH.Prelude.RAM

Contents

Description

RAM primitives with a combinational read port.

Synopsis

RAM synchronised to the system clock

asyncRam Source #

Arguments

:: Enum addr 
=> SNat n

Size n of the RAM

-> Signal addr

Read address r

-> Signal (Maybe (addr, a))

(write address w, value to write)

-> Signal a

Value of the RAM at address r

Create a RAM with space for n elements.

Additional helpful information:

asyncRamPow2 Source #

Arguments

:: KnownNat n 
=> Signal (Unsigned n)

Read address r

-> Signal (Maybe (Unsigned n, a))

(write address w, value to write)

-> Signal a

Value of the RAM at address r

Create a RAM with space for 2^n elements

Additional helpful information:

RAM synchronised to an arbitrary clock

asyncRam' Source #

Arguments

:: Enum addr 
=> SClock wclk

Clock to which to synchronise the write port of the RAM

-> SClock rclk

Clock to which the read address signal, r, is synchronised

-> SNat n

Size n of the RAM

-> Signal' rclk addr

Read address r

-> Signal' wclk (Maybe (addr, a))

(write address w, value to write)

-> Signal' rclk a

Value of the RAM at address r

Create a RAM with space for n elements

Additional helpful information:

asyncRamPow2' Source #

Arguments

:: KnownNat n 
=> SClock wclk

Clock to which to synchronise the write port of the RAM

-> SClock rclk

Clock to which the read address signal, r, is synchronised

-> Signal' rclk (Unsigned n)

Read address r

-> Signal' wclk (Maybe (Unsigned n, a))

(write address w, value to write)

-> Signal' rclk a

Value of the RAM at address r

Create a RAM with space for 2^n elements

Additional helpful information:

Internal

asyncRam# Source #

Arguments

:: SClock wclk

Clock to which to synchronise the write port of the RAM

-> SClock rclk

Clock to which the read address signal, r, is synchronised

-> SNat n

Size n of the RAM

-> Signal' rclk Int

Read address r

-> Signal' wclk Bool

Write enable

-> Signal' wclk Int

Write address w

-> Signal' wclk a

Value to write (at address w)

-> Signal' rclk a

Value of the RAM at address r

RAM primitive