Clash.Prelude.RAM

RAM primitives with a combinational read port.

RAM synchronised to an arbitrary clock

asyncRam

Arguments

:: (Enum addr, HiddenClock domain gated, HasCallStack)

=> SNat n

Size n of the RAM

-> Signal domain addr

Read address r

-> Signal domain (Maybe (addr, a))

(write address w, value to write)

-> Signal domain a

Value of the RAM at address r

Create a RAM with space for n elements.

• NB: Initial content of the RAM is undefined

Additional helpful information:

• See Clash.Prelude.BlockRam for more information on how to use a RAM.

asyncRamPow2

Arguments

:: (KnownNat n, HiddenClock domain gated, HasCallStack)

=> Signal domain (Unsigned n)

Read address r

-> Signal domain (Maybe (Unsigned n, a))

(write address w, value to write)

-> Signal domain a

Value of the RAM at address r

Create a RAM with space for 2^n elements

• NB: Initial content of the RAM is undefined

Additional helpful information:

• See Clash.Prelude.BlockRam for more information on how to use a RAM.