clash-prelude-0.99.2: CAES Language for Synchronous Hardware - Prelude library

Copyright(C) 2015-2016 University of Twente
2017 Google Inc.
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <christiaan.baaij@gmail.com>
Safe HaskellSafe
LanguageHaskell2010
Extensions
  • DataKinds
  • MagicHash
  • TypeOperators
  • ExplicitNamespaces

Clash.Explicit.ROM

Contents

Description

ROMs

Synopsis

Synchronous ROM synchronised to an arbitrary clock

rom Source #

Arguments

:: (KnownNat n, Enum addr) 
=> Clock domain gated

Clock to synchronize to

-> Vec n a

ROM content

NB: must be a constant

-> Signal domain addr

Read address rd

-> Signal domain a

The value of the ROM at address rd from the previous clock cycle

A ROM with a synchronous read port, with space for n elements

  • NB: Read value is delayed by 1 cycle
  • NB: Initial output value is undefined

Additional helpful information:

romPow2 Source #

Arguments

:: KnownNat n 
=> Clock domain gated

Clock to synchronize to

-> Vec (2 ^ n) a

ROM content

NB: must be a constant

-> Signal domain (Unsigned n)

Read address rd

-> Signal domain a

The value of the ROM at address rd

A ROM with a synchronous read port, with space for 2^n elements

  • NB: Read value is delayed by 1 cycle
  • NB: Initial output value is undefined

Additional helpful information:

Internal

rom# Source #

Arguments

:: KnownNat n 
=> Clock domain gated

Clock to synchronize to

-> Vec n a

ROM content

NB: must be a constant

-> Signal domain Int

Read address rd

-> Signal domain a

The value of the ROM at address rd from the previous clock cycle

ROM primitive