clash-prelude-0.99.2: CAES Language for Synchronous Hardware - Prelude library

Copyright(C) 2015-2016 University of Twente
2017 Myrtle Software Ltd Google Inc.
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <christiaan.baaij@gmail.com>
Safe HaskellSafe
LanguageHaskell2010
Extensions
  • Cpp
  • MonoLocalBinds
  • ScopedTypeVariables
  • BangPatterns
  • TypeFamilies
  • DataKinds
  • FlexibleContexts
  • MagicHash
  • KindSignatures
  • TypeOperators
  • ExplicitNamespaces
  • ExplicitForAll
  • TypeApplications

Clash.Prelude.RAM

Contents

Description

RAM primitives with a combinational read port.

Synopsis

RAM synchronised to an arbitrary clock

asyncRam Source #

Arguments

:: (Enum addr, HiddenClock domain gated, HasCallStack) 
=> SNat n

Size n of the RAM

-> Signal domain addr

Read address r

-> Signal domain (Maybe (addr, a))

(write address w, value to write)

-> Signal domain a

Value of the RAM at address r

Create a RAM with space for n elements.

Additional helpful information:

asyncRamPow2 Source #

Arguments

:: (KnownNat n, HiddenClock domain gated, HasCallStack) 
=> Signal domain (Unsigned n)

Read address r

-> Signal domain (Maybe (Unsigned n, a))

(write address w, value to write)

-> Signal domain a

Value of the RAM at address r

Create a RAM with space for 2^n elements

Additional helpful information: