Clash.Explicit.DDR

We simulate DDR signal by using Signals which have exactly half the period (or double the speed) of our normal Signals.

The primives in this module can be used to produce of consume DDR signals.

DDR signals are not meant to be used internally in a design, but only to communicate with the outside world.

In some cases hardware specific DDR IN registers can be infered by synthesis tools from these generic primitives. But to be sure your design will synthesize to dedicated hardware resources use the functions from Clash.Intel.DDR or Clash.Xilinx.DDR.

Documentation

ddrIn

Arguments

:: (HasCallStack, fast ~ Dom n pFast, slow ~ Dom n (2 * pFast))

=> Clock slow gated

clock

-> Reset slow synchronous

reset

-> (a, a, a)

reset values

-> Signal fast a

DDR input signal

-> Signal slow (a, a)

normal speed output pairs

DDR input primitive

Consumes a DDR input signal and produces a regular signal containing a pair of values.

ddrOut

Arguments

:: (HasCallStack, fast ~ Dom n pFast, slow ~ Dom n (2 * pFast))

=> Clock slow gated

clock

-> Reset slow synchronous

reset

-> a

reset value

-> Signal slow (a, a)

normal speed input pairs

-> Signal fast a

DDR output signal

DDR output primitive

Produces a DDR output signal from a normal signal of pairs of input.

Internal

ddrIn# :: forall a slow fast n pFast gated synchronous. (HasCallStack, fast ~ Dom n pFast, slow ~ Dom n (2 * pFast)) => Clock slow gated -> Reset slow synchronous -> a -> a -> a -> Signal fast a -> Signal slow (a, a)

ddrOut# :: (HasCallStack, fast ~ Dom n pFast, slow ~ Dom n (2 * pFast)) => Clock slow gated -> Reset slow synchronous -> a -> Signal slow a -> Signal slow a -> Signal fast a