clash-prelude-0.9999: CAES Language for Synchronous Hardware - Prelude library
Copyright(C) 2015-2016 University of Twente
2017 Google Inc.
2019 Myrtle Software Ltd
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <christiaan.baaij@gmail.com>
Safe HaskellTrustworthy
LanguageHaskell2010
Extensions
  • MonoLocalBinds
  • ScopedTypeVariables
  • GADTs
  • GADTSyntax
  • DataKinds
  • MagicHash
  • RankNTypes
  • TypeOperators
  • ExplicitNamespaces
  • ExplicitForAll

Clash.Explicit.ROM

Description

ROMs

Synopsis

Synchronous ROM synchronized to an arbitrary clock

rom Source #

Arguments

:: (KnownDomain dom, KnownNat n, Undefined a, Enum addr) 
=> Clock dom

Clock to synchronize to

-> Enable dom

Global enable

-> Vec n a

ROM content

NB: must be a constant

-> Signal dom addr

Read address rd

-> Signal dom a

The value of the ROM at address rd from the previous clock cycle

A ROM with a synchronous read port, with space for n elements

  • NB: Read value is delayed by 1 cycle
  • NB: Initial output value is undefined

Additional helpful information:

romPow2 Source #

Arguments

:: (KnownDomain dom, KnownNat n, Undefined a) 
=> Clock dom

Clock to synchronize to

-> Enable dom

Global enable

-> Vec (2 ^ n) a

ROM content

NB: must be a constant

-> Signal dom (Unsigned n)

Read address rd

-> Signal dom a

The value of the ROM at address rd

A ROM with a synchronous read port, with space for 2^n elements

  • NB: Read value is delayed by 1 cycle
  • NB: Initial output value is undefined

Additional helpful information:

Internal

rom# Source #

Arguments

:: forall dom n a. (KnownDomain dom, KnownNat n, Undefined a) 
=> Clock dom

Clock to synchronize to

-> Enable dom

Global enable

-> Vec n a

ROM content

NB: must be a constant

-> Signal dom Int

Read address rd

-> Signal dom a

The value of the ROM at address rd from the previous clock cycle

ROM primitive