clash-prelude-1.5.0: Clash: a functional hardware description language - Prelude library
Copyright(C) 2015-2016 University of Twente
2017 Google Inc.
2019 Myrtle Software Ltd
2021 QBayLogic B.V.
LicenseBSD2 (see the file LICENSE)
MaintainerQBayLogic B.V. <devops@qbaylogic.com>
Safe HaskellTrustworthy
LanguageHaskell2010
Extensions
  • Cpp
  • MonoLocalBinds
  • ScopedTypeVariables
  • BangPatterns
  • TypeFamilies
  • ViewPatterns
  • DataKinds
  • InstanceSigs
  • StandaloneDeriving
  • DeriveDataTypeable
  • DeriveFunctor
  • DeriveTraversable
  • DeriveFoldable
  • DeriveGeneric
  • DefaultSignatures
  • DeriveLift
  • DerivingStrategies
  • FlexibleContexts
  • MagicHash
  • KindSignatures
  • TupleSections
  • TypeOperators
  • ExplicitNamespaces
  • ExplicitForAll
  • BinaryLiterals
  • TypeApplications

Clash.Explicit.RAM

Description

RAM primitives with a combinational read port.

Synopsis

RAM synchronized to an arbitrary clock

asyncRam Source #

Arguments

:: (Enum addr, HasCallStack, KnownDomain wdom, KnownDomain rdom) 
=> Clock wdom

Clock to which to synchronize the write port of the RAM

-> Clock rdom

Clock to which the read address signal, r, is synchronized to

-> Enable wdom

Global enable

-> SNat n

Size n of the RAM

-> Signal rdom addr

Read address r

-> Signal wdom (Maybe (addr, a))

(write address w, value to write)

-> Signal rdom a

Value of the RAM at address r

Create a RAM with space for n elements

Additional helpful information:

asyncRamPow2 Source #

Arguments

:: forall wdom rdom n a. (KnownNat n, HasCallStack, KnownDomain wdom, KnownDomain rdom) 
=> Clock wdom

Clock to which to synchronize the write port of the RAM

-> Clock rdom

Clock to which the read address signal, r, is synchronized

-> Enable wdom

Global enable

-> Signal rdom (Unsigned n)

Read address r

-> Signal wdom (Maybe (Unsigned n, a))

(write address w, value to write)

-> Signal rdom a

Value of the RAM at address r

Create a RAM with space for 2^n elements

Additional helpful information:

Internal

asyncRam# Source #

Arguments

:: (HasCallStack, KnownDomain wdom, KnownDomain rdom) 
=> Clock wdom

Clock to which to synchronize the write port of the RAM

-> Clock rdom

Clock to which the read address signal, r, is synchronized

-> Enable wdom

Global enable

-> SNat n

Size n of the RAM

-> Signal rdom Int

Read address r

-> Signal wdom Bool

Write enable

-> Signal wdom Int

Write address w

-> Signal wdom a

Value to write (at address w)

-> Signal rdom a

Value of the RAM at address r

RAM primitive