úÎA\;Ie      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcd'non-portable (requires IA-32 processor) provisionalmartin@grabmueller.dew(features as found in page 1, register D e(features as found in page 1, register C fProcessor information. Processor family. Processor model. Processor stepping.  !Information for caches and TLBs. Prefetching information. 2Trace cache (1st-level code cache) configuration. "Second-level cache configuration. Internal use only. No third level support. "Second-level cache configuration. No second level support. &First-level code cache configuration. &First-level code cache configuration. Configuration of data TLB. Configuration of code TLB. ACache associativity. For some entries, this is not specified in ! the manual. We report these as . Bytes per sector in a cache. Line size in a cache. ;Cache size. Some entries can have alternative cache sizes, ! therefore the complicated type. 9Page size. Some entries can have alternative page sizes, ! therefore the complicated type. !"#MuOps in a processors trace cache. #$*Associativity in a set-associative cache. %&Number of entries in a TLB. 'g( Execute the cpuid& instructions with the given argument : in the EAX register. Return the values of the registers & EAX, EBX, ECX and EDX in that order. hRun cpuid@ but check before that the used operation is actually supported i) Execute the cpuid# instruction and return the vendor & string reported by that instruction. * Execute the cpuid) instruction and return the brand string 9 (processor name and maximum frequency) reported by that  instruction. +@Fetch all available cache information from the processor, using  the cpuid( instruction. The list is not ordered. j0Convert the strange 0x40 code to valid entries. kDConvert the values from the registers to cache information records. lConvert kBytes to bytes. mConvert mBytes to bytes. n:Table of cache configuration. Information from the CPUID  documentation in the /+IA-32 Intel Architecture Software Developer's  Manual Volumes 2A/. ,BRetrieve basic processor information from the processor using the  cpuid instruction. oNInstead of ProcessorInfo we could also export this FlagSet and the accessors. 'This would be more space efficient and <would also allow for construction of processor identifiers. pNInstead of ProcessorInfo we could also export this FlagSet and the accessors. 'This would be more space efficient and <would also allow for construction of processor identifiers. qNInstead of ProcessorInfo we could also export this FlagSet and the accessors. 'This would be more space efficient and <would also allow for construction of processor identifiers. rNInstead of ProcessorInfo we could also export this FlagSet and the accessors. 'This would be more space efficient and <would also allow for construction of processor identifiers. sNInstead of ProcessorInfo we could also export this FlagSet and the accessors. 'This would be more space efficient and <would also allow for construction of processor identifiers. t-.uv/0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcde  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcde(,)*+! $%&'  "#-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcde  ! !"##$%%&''()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdw       !!"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmno cpuid-0.2.2 System.Cpuid Feature1D Feature1CFlagSet ProcessorInfopiFamilypiModel piSteppingpiType CacheInfo Prefetching TraceCacheThirdLevelCacheNoSecondOrThirdLevelCacheNoThirdLevelCacheSecondLevelCacheNoSecondLevelCacheFirstLevelDCacheFirstLevelICacheDataTLBInstructionTLB Associativity DirectMappedSetAssociativeBytesPerSectorLineSize CacheSize CacheSizeOrPageSize PageSizeOrMuOpsWaysEntriescpuid vendorString brandString cacheInfo processorInfofeaturestestFlagsse3 pclmulqdqdtes64monitordscplvmxsmxesttm2ssse3cnxtidfma cmpxchg16bxtprpdcmdcasse4_1sse4_2x2apicmovbepopcntaesxsaveosxsaveavxfpuvmedepsetscmsrpaemcecx8apicsepmtrrpgemcacmovpatpse36psnclfshdsacpimmxfxsrssesse2sshtttmpbecpuid_ cpuidMaybepeekCStringLen postProcess interpretCDkBytemByte cacheTablesteppingmodel baseFamilytyp extFamilyfamily*-> showsPrecEnum