h&r      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}(c) 2008,2010 Martin Grabmueller (c) 2011 Henning ThielemannGPLmartin@grabmueller.de provisional'non-portable (requires IA-32 processor) Safe-Inferred *cpuid'features as found in page 1, register Dcpuid'features as found in page 1, register CcpuidProcessor information.cpuidProcessor family.cpuidProcessor model.cpuidProcessor stepping. cpuid Information for caches and TLBs. cpuidConfiguration of code TLB. cpuidConfiguration of data TLB. cpuid%First-level code cache configuration. cpuid%First-level code cache configuration.cpuidNo second level support.cpuid!Second-level cache configuration.cpuidNo third level support.cpuidInternal use only.cpuid!Second-level cache configuration.cpuid1Trace cache (1st-level code cache) configuration.cpuidPrefetching information.cpuidCache associativity. For some entries, this is not specified in the manual. We report these as .cpuidBytes per sector in a cache.cpuidLine size in a cache.cpuidCache size. Some entries can have alternative cache sizes, therefore the complicated type.cpuidPage size. Some entries can have alternative page sizes, therefore the complicated type."cpuid"MuOps in a processors trace cache.$cpuid)Associativity in a set-associative cache.&cpuidNumber of entries in a TLB.(cpuid Execute the cpuid instructions with the given argument in the EAX register. Return the values of the registers EAX, EBX, ECX and EDX in that order.~cpuidRun cpuid? but check before that the used operation is actually supported)cpuid Execute the cpuid instruction and return the vendor string reported by that instruction.*cpuid Execute the cpuid instruction and return the brand string (processor name and maximum frequency) reported by that instruction.+cpuidFetch all available cache information from the processor, using the cpuid' instruction. The list is not ordered.cpuid/Convert the strange 0x40 code to valid entries.cpuidConvert the values from the registers to cache information records.cpuidConvert kBytes to bytes.cpuidConvert mBytes to bytes.cpuidTable of cache configuration. Information from the CPUID documentation in the /IA-32 Intel Architecture Software Developer's Manual Volumes 2A/.,cpuidRetrieve basic processor information from the processor using the cpuid instruction.cpuidInstead of ProcessorInfo we could also export this FlagSet and the accessors. This would be more space efficient and would also allow for construction of processor identifiers.cpuidInstead of ProcessorInfo we could also export this FlagSet and the accessors. This would be more space efficient and would also allow for construction of processor identifiers.cpuidInstead of ProcessorInfo we could also export this FlagSet and the accessors. This would be more space efficient and would also allow for construction of processor identifiers.cpuidInstead of ProcessorInfo we could also export this FlagSet and the accessors. This would be more space efficient and would also allow for construction of processor identifiers.cpuidInstead of ProcessorInfo we could also export this FlagSet and the accessors. This would be more space efficient and would also allow for construction of processor identifiers.  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghij(,)*+ !$%&' "#-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghij9        !!"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~#cpuid-0.2.3.1-ur1ERbOn3u3mfa2wNovCi System.Cpuid Feature1D Feature1CFlagSet ProcessorInfopiFamilypiModel piSteppingpiType CacheInfoInstructionTLBDataTLBFirstLevelICacheFirstLevelDCacheNoSecondLevelCacheSecondLevelCacheNoThirdLevelCacheNoSecondOrThirdLevelCacheThirdLevelCache TraceCache Prefetching AssociativitySetAssociative DirectMappedBytesPerSectorLineSize CacheSize CacheSizeOrPageSize PageSizeOrMuOpsWaysEntriescpuid vendorString brandString cacheInfo processorInfofeaturestestFlagsse3 pclmulqdqdtes64monitordscplvmxsmxesttm2ssse3cnxtidfma cmpxchg16bxtprpdcmpciddcasse4_1sse4_2x2apicmovbepopcntdeadlineaesxsaveosxsaveavxf16crdrand hypervisorfpuvmedepsetscmsrpaemcecx8apicsepmtrrpgemcacmovpatpse36psnclfshdsacpimmxfxsrssesse2sshtttmia64pbe$fShowFeature1C$fBoundedFeature1C$fEnumFeature1C$fShowFeature1D$fBoundedFeature1D$fEnumFeature1D $fEqFeature1D$fOrdFeature1D $fEqFeature1C$fOrdFeature1C$fShowCacheInfo$fShowAssociativity$fShowBytesPerSector$fShowLineSize$fShowCacheSize$fShowPageSize $fShowMuOps $fShowWays $fShowEntries cpuidMaybe postProcess interpretCDkBytemByte cacheTablesteppingmodel baseFamilytyp extFamily*->