úÎ'$’*      !"#$%&'()'non-portable (requires IA-32 processor) provisionalmagr@cs.tu-berlin.de1*Processor information. Processor family. Processor model. Processor stepping. !Information for caches and TLBs. Prefetching information. 2Trace cache (1st-level code cache) configuration. "Second-level cache configuration. Internal use only. No third level support. "Second-level cache configuration. No second level support. &First-level code cache configuration. &First-level code cache configuration. Configuration of data TLB. Configuration of code TLB. ACache associativity. For some entries, this is not specified in ! the manual. We report these as . Bytes per sector in a cache. Line size in a cache. ;Cache size. Some entries can have alternative cache sizes, ! therefore the complicated type. 9Page size. Some entries can have alternative page sizes, ! therefore the complicated type. #MuOps in a processors trace cache. !*Associativity in a set-associative cache. "#Number of entries in a TLB. $% Execute the cpuid& instructions with the given argument : in the EAX register. Return the values of the registers & EAX, EBX, ECX and EDX in that order. & Execute the cpuid# instruction and return the vendor & string reported by that instruction. ' Execute the cpuid) instruction and return the brand string 9 (processor name and maximum frequency) reported by that  instruction. (@Fetch all available cache information from the processor, using  the cpuid( instruction. The list is not ordered. + Call the cpuid6 instruction as often as needed and merge the values. ,0Convert the strange 0x40 code to valie entries. -;Convert the values from the registers to cache information  records. .Convert kBytes to bytes. /Convert mBytes to bytes. 0:Table of cache configuration. Information from the CPUID  documentation in the /+IA-32 Intel Architecture Software Developer's  Manual Volumes 2A/. )BRetrieve basic processor information from the processor using the  cpuid instruction. *  !"#$%&'()*!"#$  %)&'(*    !""#$$%&'()1      !"#$%&'()*+ cpuid-0.2 System.Cpuid ProcessorInfopiFamilypiModel piSteppingpiType CacheInfo Prefetching TraceCacheThirdLevelCacheNoSecondOrThirdLevelCacheNoThirdLevelCacheSecondLevelCacheNoSecondLevelCacheFirstLevelDCacheFirstLevelICacheDataTLBInstructionTLB Associativity DirectMappedSetAssociativeBytesPerSectorLineSize CacheSize CacheSizeOrPageSize PageSizeOrMuOpsWaysEntriescpuid vendorString brandString cacheInfo processorInfo_cpuidcollectCacheDescriptors postProcessupdateCDkBytemByte cacheTable