úÎ2Ò0&3      !"#$%&'()*+,-./012portable provisional*martin@grabmueller.de,klee@cs.tu-berlin.de Safe-Infered&3Instructions can be displayed either in Intel or AT&T style (like in  GNU tools).  Intel style: 1 Destination operand comes first, source second. $ No register or immediate prefixes. 2 Memory operands are annotated with operand size. ' Hexadecimal numbers are suffixed with H and prefixed with 0 if  necessary. AT& T style: 1 Source operand comes first, destination second. " Register names are prefixes with %.  Immediates are prefixed with $. ' Hexadecimal numbers are prefixes with 0x C Opcodes are suffixed with operand size, when ambiguous otherwise.  Show in AT&T style Show in Intel style EThe disassembly routines return lists of the following datatype. It F encodes both invalid byte sequences (with a useful error message, if G possible), or a valid instruction. Both variants contain the list of H opcode bytes from which the instruction was decoded and the address of  the instruction. Valid instruction Opcode of the instruction Operand size, if any Instruction operands Start address of instruction Instruction bytes Pseudo instruction, e.g. label Invalid instruction FSome opcodes can operate on data of several widths. This information C is encoded in instructions using the following enumeration type.. 80-bit floating point operand 64-bit floating point operand 32-bit floating point operand 128-bit integer operand 64-bit integer operand 32-bit integer operand 16-bit integer operand 8-bit integer operand No operand size specified 4All operands are in one of the following locations: % Constants in the instruction stream  Memory locations  Registers DMemory locations are referred to by on of several addressing modes: * Absolute (address in instruction stream) ) Register-indirect (address in register) % Register-indirect with displacement  Base-Index with scale ) Base-Index with scale and displacement >Displacements can be encoded as 8 or 32-bit immediates in the @ instruction stream, but are encoded as Int in instructions for  simplicity. )Base plus scaled index with displacement Scaled index with displacement Base plus scaled index !$Register-indirect with displacement "Register-indirect #Floating-point register $ Register %Absolute address &Immediate value '6All opcodes are represented by this enumeration type. ($Show an instruction in Intel style. )Show an instruction in AT& T style. *9Disassemble a block of memory. Starting at the location @ pointed to by the given pointer, the given number of bytes are  disassembled. ,-Disassemble the contents of the given array. .,Disassemble the contents of the given list. 4  !"#$%&'()*+,-./01233  !"#$%&'()*+,-./0123'&%$#"!    *.,0+/-1()2     &%$#"! '()*+,-./01234       !"#$%&'()*+,-./01234disassembler-0.2.0.0!Text.Disassembler.X86DisassemblerConfigconfDefaultBitModeconfOperandBitModeconfAddressBitModeconfIn64BitMode confStartAddr ShowStyleAttStyle IntelStyle InstructionopcodeopsizeoperandsaddressbytesPseudoInstructionBadInstructionInstrOperandSizeOPF80OPF64OPF32OP128OP64OP32OP16OP8OPNONEOperandOpBaseIndexDisp OpIndexDisp OpBaseIndex OpIndDispOpIndOpFPRegOpRegOpAddrOpImmOpcode showIntelshowAttdisassembleBlockdisassembleBlockWithConfigdisassembleArraydisassembleArrayWithConfigdisassembleListdisassembleListWithConfigdisassembleFiledisassembleFileWithConfig defaultConfig$fShowInstruction