rM#3      !"#$%&'()*+,-./012)(c) Martin Grabmueller and Dirk KleeblattBSD3*martin@grabmueller.de,klee@cs.tu-berlin.de provisionalportableNone3(QInstructions can be displayed either in Intel or AT&T style (like in GNU tools). Intel style:/Destination operand comes first, source second."No register or immediate prefixes.0Memory operands are annotated with operand size.&Hexadecimal numbers are suffixed with H and prefixed with 0 if necessary. AT&T style:/Source operand comes first, destination second.!Register names are prefixes with %.Immediates are prefixed with $.&Hexadecimal numbers are prefixes with 0xAOpcodes are suffixed with operand size, when ambiguous otherwise.Show in AT&T style Show in Intel style +The disassembly routines return lists of the following datatype. It encodes both invalid byte sequences (with a useful error message, if possible), or a valid instruction. Both variants contain the list of opcode bytes from which the instruction was decoded and the address of the instruction. Valid instruction Opcode of the instruction Operand size, if anyInstruction operandsStart address of instructionInstruction bytesPseudo instruction, e.g. labelInvalid instructionSome opcodes can operate on data of several widths. This information is encoded in instructions using the following enumeration type..80-bit floating point operand64-bit floating point operand32-bit floating point operand128-bit integer operand64-bit integer operand32-bit integer operand16-bit integer operand8-bit integer operandNo operand size specified3Encodes the default and currently active operand or address size. Can be changed with the operand- or address-size prefixes 0x66 and 0x67.3All operands are in one of the following locations:#Constants in the instruction streamMemory locations RegistersCMemory locations are referred to by on of several addressing modes:(Absolute (address in instruction stream)'Register-indirect (address in register)#Register-indirect with displacementBase-Index with scale'Base-Index with scale and displacement Displacements can be encoded as 8 or 32-bit immediates in the instruction stream, but are encoded as Int in instructions for simplicity.(Base plus scaled index with displacementScaled index with displacement Base plus scaled index!#Register-indirect with displacement"Register-indirect#Floating-point register$Register%Absolute address&Immediate value'5All opcodes are represented by this enumeration type.(#Show an instruction in Intel style.)"Show an instruction in AT&T style.*Disassemble a block of memory. Starting at the location pointed to by the given pointer, the given number of bytes are disassembled.,,Disassemble the contents of the given array..+Disassemble the contents of the given list.4hTest function for disassembling the contents of a binary file and displaying it in the provided style ( IntelStyle or AttStyle).56789:;<= >?@ 3AB !"#$%&'CDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~()*+,-./0142      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~3  !"#$%&'()*+,-./0123'&%$#"!    *.,0+/-1()2"56789:;<= >@?   3BA &%$#"! '~}|{zyxwvutsrqponmlkjihgfedcba`_^]\[ZYXWVUTSRQPONMLKJIHGFEDCBA@?>=<;:9876543210/.-,+*)('&%$#"!      ~}|{zyxwvutsrqponmlkjihgfedcba`_^]\[ZYXWVUTSRQPONMLKJIHGFEDC()*+,-./0142      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~       !"#$%&'()*+,-./01234566789:;<==>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~disassembler-0.2.0.1!Text.Disassembler.X86DisassemblerConfigconfDefaultBitModeconfOperandBitModeconfAddressBitModeconfIn64BitMode confStartAddr ShowStyleAttStyle IntelStyle InstructionopcodeopsizeoperandsaddressbytesPseudoInstructionBadInstructionInstrOperandSizeOPF80OPF64OPF32OP128OP64OP32OP16OP8OPNONEOperandOpBaseIndexDisp OpIndexDisp OpBaseIndex OpIndDispOpIndOpFPRegOpRegOpAddrOpImmOpcode showIntelshowAttdisassembleBlockdisassembleBlockWithConfigdisassembleArraydisassembleArrayWithConfigdisassembleListdisassembleListWithConfigdisassembleFiledisassembleFileWithConfig defaultConfig OperandSizetestFile Word8ParserPStatedefaultBitModeoperandBitModeaddressBitMode in64BitModeprefixes startAddrInstrBadBIT32BIT16XORPSXORPDXORXLATXCHGXADDWRMSRWBINVDWAITVMXONVMXOFFVMWRITEVMRESUMEVMREADVMPTRSTVMPTRLDVMLAUNCHVMCLEARVMCALLVERWVERRUNPCKLPSUNPCKLPDUNPCKHPSUNPCKHPDUD2UCOMISSUCOMISDTESTSYSEXITSYSENTERSYSCALLSWAPGSSUBSSSUBSDSUBPSSUBPDSUBSTRSTOSSTMXCSRSTISTDSTCSQRTSSSQRTSDSQRTPSSQRTPDSMSWSLDTSIDTSHRDSHRSHLDSHLSGDTSFENCESETSSETPSETOSETNSSETNPSETNOSETNESETNBSETLESETLSETGESETGSETESETBESETBSETASCASSBBSARSAHFRSQRTSSRSQRTPSRSMRORROLRETFRETRDTSCRDPMCRDMSRRCRRCPSSRCPPSRCLPXORPUSHFQPUSHFDPUSHFPUSHADPUSHAPUSHPSUBWPSUBUSWPSUBUSBPSUBSQPSUBSBPSUBQPSUBDPSUBBPSRLWPSRLQPSRLDQPSRLDPSRAWPSRADPSLLWPSLLQPSLLDQPSLLDPSADBW PREFETCHT2 PREFETCHT1 PREFETCHT0 PREFETCHNTAPORPOPFQPOPFDPOPFPOPADPOPAPOPPMULUDQPMULLWPMULHWPMULHUWPMOVMSKBPMINUBPMINSWPMAXUBPMAXSWPMADDWDPAVGWPAVGBPAUSEPANDNPANDPADDWPADDUSWPADDUSBPADDSWPADDSBPADDQPADDDPADDBOUTSOUTORPSORPDORNOTNOPNEGMWAITMULSSMULSDMULPSMULPDMULMOVZXWMOVZXBMOVUPSMOVUPDMOVSXWMOVSXDMOVSXBMOVSSMOVSLDUPMOVSDMOVSMOVQMOVNTQMOVNTPSMOVNTPDMOVNTDQMOVMSKPSMOVMSKPDMOVLSDUPMOVLPSMOVLPDMOVLHPSMOVHPSMOVHPDMOVDDUPMOVAPSMOVAPDMOVMONITORMINSSMINSDMINPSMINPDMFENCEMAXSSMAXSDMAXPSMAXPDMASKMOVQLTRLSSLSLLOOPNELOOPELOOPLODSLMSWLLDTLIDTLGSLGDTLFSLFENCELESLEAVELEALDSLDMXCSRLDDQULARLAHFJSJPJOJNSJNPJNOJNEJNBJMPNJMPFJMPJLEJLJGEJGJEJCXZJBEJBJAIRETINVLPGINVDINTOINT3INTINSINCINBSWAPIMULIDIVHSUBPSHSUBPDHLTHADDPSHADDPDFXSAVEFXRSTORFXCHFXAMFUCOMPPFUCOMPFUCOMIPFUCOMIFUCOMFTSTFSUBRPFSUBRFSUBPFSUBFSTSWFSTPFSTENVFSTCWFSTFSAVEFRSTORFNOPFMULPFMULFLDZFLDPIFLDLN2FLDLG2FLDL2TFLDL2EFLDENVFLDCWFLD1FLDFISUBRFISUBFISTTPFISTPPFISTPFISTFINITFIMULFILDFIDIVRFIDIVFICOMPFICOMFIADDFFREEFDIVRPFDIVRFDIVPFDIVFCOMPPFCOMPFCOMIPFCOMIFCOMFCMOVUFCMOVNUFCMOVNEFCMOVNBEFCMOVNBFCMOVEFCMOVBEFCMOVBFCLEXFCHSFBSTPFBLDFADDPFADDFABSENTEREMMSDIVSSDIVSDDIVPSDIVPDDIVDECDASDAACWDECWDCPUIDCOMISSCOMISD CMPXCHG8B CMPXCHG16BCMPXCHGCMPSCMPCMOVSCMOVPCMOVOCMOVNSCMOVNPCMOVNOCMOVNECMOVNBCMOVLECMOVLCMOVGECMOVGCMOVECMOVBECMOVBCMOVACMCCLTSCLICLFLUSHCLDCLCCDQECDQCBWCALLFCALLBTSBTRBTCBTBSRBSFBOUNDARPLANDPSANDPDANDNPSANDNPDANDADDUBPSADDSUBPDADDSSADDSDADDPSADDPDADDADCAASAAMAADAAA InvalidOpcodeshowOp showAttOps showIntelOpsopIndhex32hex8 showPosBytesenlarge opSizeSuffixshowInstrSuffixshowImm showIntelImmshowAddr showIntelAddr instrToString configToState defaultStateparseInstructionsinstructionSequence instruction toggleBitModerex_Brex_Xrex_Rrex_WhasREX hasPrefix addPrefix parsePrefixword8anyWord8anyInt8 anyWord16anyInt16 anyWord32anyInt32 anyWord64anyInt64anyWordVanyWordZanyIntZanyWordPoneByteOpCodeMapparseInvalidPrefixparseInvalidOpcode parseReservedparseUndefinedparseUnimplementedinvalidIn64BitModeonlyIn64BitModechoose64BitModechooseOperandSizechooseAddressSize parseModRM parseModRM'parseSIB parseSIB' scaleToFactorparseAddress32parseAddress32'parseALU parsePUSHSeg parsePOPSegparseGenericGvEwparseGenericGvEbparseGenericGvEvparseGenericEvGvparseGenericEbGbparseGenericEvtwoByteOpCodeMap twoByteEscape parseGenericparseGenericIbparseGenericIwparseGenericJbparseGenericJzparseINCparseDEC parsePUSHparsePOP parsePUSHA parsePOPA parseBOUND parseARPL parseMOVSXD parsePUSHImm parseIMULparseINS parseOUTS parseJccShort parseTEST parseXCHGparseMOVparseLEA parse0x90 parseXCHGRegparseCBW_CWDE_CDQEparseCWD_CDQ_CQO parseCALLF parsePUSHF parsePOPF parseJMPF parseMOVImm parseMOVS parseCMPS parseTESTImm parseSTOS parseLODS parseSCASparseMOVImmByteToByteRegparseMOVImmToReg parseRETNparseLoadSegmentRegister parseENTERparseESC parseINImm parseOUTImmparseINparseOUT registerNameinstrOperandSize regnames8 regnames16 regnames32 regnames64 segregnamesmmxregsxmmregsjccname setccname cmovccname parseGrp1aluOps parseGrp1A parseGrp2shiftOps parseGrp3 parseGrp4 parseGrp5 parseGrp6 parseGrp7 parseGrp8 parseGrp9 parseGrp10 parseGrp11mmxInstr parseGrp12 parseGrp13 parseGrp14 parseGrp15 parseGrp16 parseXmmVW parseXmmWV parseXmmGU parseMOVUPS parseMOVLPS parseUNPCKLPS parseUNPCKHPS parseMOVHPSparseMOVCtrlDebug parseMOVAPS parseCVTI2PS parseMOVNTPS parseCVTPS2PIparseCVTTPS2PI parseUCOMISS parseCOMISS parseCMOVcc parseMOVSKPS parseSQRTPS parseRSQRTPS parseRCPPS parseCVTPS2PD parseANDNPS parseANDPS parseORPS parseXORPS parseADDPS parseMULPS parseCVTDQ2PSparsePUNPCKLWD parsePACKSSWBparsePUNPCKHWD parseSUBPS parseMINPS parseDIVPS parseMAXPSparsePUNPCKLBWparsePUNPCKLDQ parsePACKUSWB parsePCMPGTB parsePCMPGTW parsePCMPGTDparsePUNPCKHBWparsePUNPCKHDQ parsePACKSSDWparsePUNPCKLQDQparsePUNPCKHQDQ parsePSHUFW parsePCMPEQB parsePCMPEQW parsePCMPEQD parseVMREAD parseVMWRITE parseHADDPS parseHSUBPS parseMOVD_Q parseJccLong parseSETcc parseSHLD parseSHRD parseCMPPS parseMOVNTI parsePINSRW parsePEXTRW parseSHUFPS parseBSWAP parseADDSUBPSparseMmxXmmPQVWparseMmxXmmMPMVparseMmxXmmPNVU parsePSRLW parsePSRLD parsePSRLQ parsePADDQ parsePMULLW parseMOVQ parsePMOVMSKB parsePSUBUSB parsePSUBUSW parsePMINUB parsePAND parsePADDUSB parsePADDUSW parsePMAXUB parsePANDN parsePAVGB parsePSRAW parsePSRAD parsePAVGW parseCVTPD2DQ parsePMULHUW parsePMULHW parseMOVNTQ parsePSUBSB parsePSUBSQ parsePMINSWparsePOR parsePADDSB parsePADDSW parsePMAXSW parsePXOR parseLDDQU parsePSLLW parsePSLLD parsePSLLQ parsePMULUDQ parsePMADDWD parsePSADBW parseMASKMOVQ parsePSUBB parsePSUBW parsePSUBD parsePSUBQ parsePADDB parsePADDW parsePADDD$fShowInstruction