Ice40.Pll.Pad

PLL Pad hard IP primitive from Lattice Ice Technology Library. The PLL pad primitive should be used when the source clock of the PLL is driven by an input pad that is located in the bottom IO bank (IO Bank 2) or the top IO bank (IO Bank 0), and the source clock is not required inside the FPGA.

Documentation

pllPadPrim

Arguments

:: KnownDomain dom'

=> BitVector 7

divf

-> BitVector 3

divq

-> BitVector 4

divr

-> String

feedbackPath

-> BitVector 3

filterRange

-> String

pllOutSelect

-> String

delayAdjustmentModeFeedback

-> String

delayAdjustmentModeRelative

-> BitVector 4

fdaFeedback

-> BitVector 4

fdaRelative

-> Bit

enableIceGate

-> Clock dom

packagePin

-> Signal dom (BitVector 8)

dynamicDelay

-> Signal dom Bit

resetb

-> Signal dom Bit

bypass

-> (Clock dom', Clock dom', Signal dom' Bool)

(pllOutCore, globalOutCore, lock)

PLL Pad primitive