h&od      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  Safe-Inferred )*;=?io-simThe identifier of this var.io-simLabel.io-simThe var's current valueio-simA stack of undo values. This is only used while executing a transaction.io-simThread Ids of threads blocked on a read of this var. It is represented in reverse order of thread wakeup, without duplicates.To avoid duplicates efficiently, the operations rely on a copy of the thread Ids represented as a set.io-sim&The vector clock of the current value.io-simCallback to construct a trace which will be attached to the dynamic trace.io-sim A thread id.IOSimPOR:  indicates that this thread is taken into account when discovering races. A thread is marked as racy iff > was executed in it or it's a thread forked by a racy thread.) Safe-Inferredio-sim&&| is a replacement for .&&. that evaluates its arguments in parallel. |&&| does NOT label its result as an IO property, unless one of its arguments is--which .&&. does. This means that using .&&. inside an argument to conjoinPar limits parallelism, while |&&| does not.11 Safe-Inferredio-sim#An exception thrown to a thread by ' to interrupt a timed-out computation.io-simunsafeTimeout n a forces the evaluation of a, with a time limit of n microseconds.io-sim Safe-Inferred Pio-simAn  aggregates effects performed by a thread. Only used by *IOSimPOR*.  Safe-Inferred   Safe-Inferred io-sim A default  MonadMVar implementation is based on 's. An MVar guarantees fairness.Implementation details: does not guarantee fairness, instead it provide compositionally. Fairness of  and < is provided by tracking queue of blocked operation in the , e.g. when a  is scheduled on a full , the request is put on to the back of the queue together with a wakeup var. When  executes, it returns the value and is using the first element of the queue to set the new value of the  and signals next  operation to unblock. This has an effect as if all the racing  calls where executed in turns. Note that readMVar has interesting semantics: it is guaranteed to read the next value put using putMVar, and all readers will wake up, not just the first. To support this, the implementation uses two queues in the empty MVar case: one for threads blocked on takeMVar", and one for threads blocked on readMVar. The putMVar< has to wake up all readers and the first "taker" (if any).io-sim when the ' is empty, guarantees to receive next putMVar' value. It will also not block if the 9 is full, even if there are other threads attempting to putMVar.* Safe-Inferred8io-simA cons list with polymorphic nil. Void a is an infinite stream () a is isomorphic to [a]Usually used with a being a non empty sum type. io-simPretty print a .      Safe-Inferred'*8;?7io-simRace exploration options. io-simThis is an upper bound on the number of schedules with race reversals that will be explored; a bound of zero means that the default schedule will be explored, but no others. Setting the bound to zero makes IOSimPOR behave rather like IOSim, in that only one schedule is explored, but (a) IOSimPOR is considerably slower, because it still collects information on potential races, and (b) the IOSimPOR schedule is different (based on priorities, in contrast to IOSim's round-robin), and plays better with shrinking.The default value is `100`.!io-simThe branching factor. This is the number of alternative schedules that IOSimPOR tries to run, per race reversal. With the default parameters, IOSimPOR will try to reverse the first 33 (100 div 3) races discovered using the default schedule, then (if 33 or more races are discovered), for each such reversed race, will run the reversal and try to reverse two more races in the resulting schedule. A high branching factor will explore more combinations of reversing fewer races, within the overall schedule bound. A branching factor of one will explore only schedules resulting from a single race reversal (unless there are fewer races available to be reversed than the schedule bound).The default value is `3`."io-simLimit on the computation time allowed per scheduling step, for catching infinite loops etc.The default value is .#io-simA schedule to replay.The default value is .io-simExecution step is identified by the thread id and a monotonically increasing number (thread specific).$io-sim9A schedule modification inserted at given execution step.&io-simStep at which the $ is activated.'io-sim)+ at the activation step. It is needed by extendScheduleControl> when combining the discovered schedule with the initial one.(io-simSeries of steps which are executed at the target step. This *includes* the target step, not necessarily as the last step.)io-simModified execution schedule.*io-simdefault scheduling mode+io-simif the current control is +, the normal scheduling will proceed, until the thread found in the first $ reaches the given step. At this point the thread is put to sleep, until after all the steps are followed.,io-simfollow the steps then continue with schedule modifications. This control is set by  followControl when controlTargets returns true.io-sim(Executing in the context of a top level .io-sim Executing in the context of the left hand side of a branch. A right branch is represented by a frame containing empty statement.io-simA branch indicates that an alternative statement is available in the current context. For example,  has two alternative statements, say "left" and "right". While executing the left statement,  branch indicates that the right branch is still available, in case the left statement fails.io-sim statement with its right alternative.io-sim statement with the  handler.io-simUnlike the other two branches, the no-op branch is not an explicit part of the STM syntax. It simply indicates that there are no alternative statements left to be executed. For example, when running right alternative of the 3 statement or when running the catch handler of a  statement, there are no alternative statements available. This case is represented by the no-op branch.io-simResult of an STM computation.io-simA committed transaction reports the vars that were written (in order of first write) so that the scheduler can unblock other threads that were blocked in STM transactions that read any of these vars.It reports the vars that were read, so we can update vector clocks appropriately.The third list of vars is ones that were created during this transaction. This is useful for an implementation of .0It also includes the updated TVarId name supply.io-simA blocked transaction reports the vars that were read so that the scheduler can block the thread on those vars.io-simAn aborted transaction reports the vars that were read so that the vector clock can be updated.-io-simA labelled value. For example  or  will insert a label to  (or ).1io-sim"Events recorded by the simulation.2io-simhold value of 3io-simhold a dynamic value of  4io-simmasking state changed5io-simthrow exception6io-simthrow asynchronous exception ()7io-simthe thread which executed  is blocked8io-simthe thread which executed  is woken up9io-sima target thread of / unmasked its exceptions, this is paired with 8# for threads which were blocked on :io-simforked a thread;io-simthread terminated normally<io-sim+thread terminated by an unhandled exception=io-simcommitted STM transaction?io-sim STM transaction blocked (due to )@io-simchanged vars causing retryAio-sim0unblocked threads by a committed STM transactionBio-simthread delayedCio-simthread woken up after a delayDio-simnew timeout created (via )Eio-sim timeout firedFio-simregistered delay (via )Gio-simregistered delay firedHio-sima new  created (via v)Iio-sima  was updated (via  updateTimeout)Jio-sima  was cancelled (via x)Kio-sima  firedLio-simevent traced when  threadStatus is executedMio-simIOSimPOR; event: new execution started exploring the given schedule.Nio-simIOSimPOR event: the labelling thread was runnable, but its execution was delayed, until O.Event inserted to mark a difference between a failed trace and a similar passing trace.Oio-simIOSimPOR1 event: marks when the thread was rescheduled by IOSimPORPio-simIOSim and IOSimPOR event: a thread was descheduledQio-simIOSimPOR event: following given scheduleRio-simIOSimPOR3 event: thread delayed to follow the given scheduleSio-simIOSimPOR( event: perform action of the given stepUio-simA type alias for i; simulation trace. It comes with useful pattern synonyms.Vio-simA result type of a simulation.Wio-sim Return value of the main thread.Xio-sim$Exception thrown by the main thread.Yio-simDeadlock discovered in the simulation. Deadlocks are discovered if simply the simulation cannot do any progress in a given time slot and there's no event which would advance the time.Zio-simOnly returned by IOSimPOR) when a step execution took longer than " was exceeded.[io-simTrace0 is a recursive data type, it is the trace of a i computation. The trace will contain information about thread scheduling, blocking on 's, and other internal state changes of i. More importantly it also supports traces generated by the computation with  (which corresponds to using  in ),  traceEventM$, or dynamically typed traces with q (which generalise the base library  )1It also contains information on discovered races. See also: , , ,  and .\io-simUsed when using i.]io-simOnly used for IOSimPOR^io-simOnly used for IOSimPORdio-simWrapper for Eventlog markers so they can be retrieved from the trace with selectTraceEventsDynamic.fio-simWrapper for Eventlog events so they can be retrieved from the trace with selectTraceEventsDynamic.io-sim a timeoutio-sima negative timeoutqio-simi has the ability to story any 6 value in its trace which can then be recovered with selectTraceEventsDynamic or selectTraceEventsDynamic`.rio-sim"Trace a value, in the same was as q does, but from the 0 monad. This is primarily useful for debugging.sio-simLift an  computation to i.Note: you can use  to lift  computations, this is just a more convenient function just for i.tio-sim>Set the current wall clock time for the thread's clock domain.uio-simPut the thread into a new wall clock domain, not shared with the parent thread. Changing the wall clock time in the new clock domain will not affect the other clock of other threads. All threads forked by this thread from this point onwards will share the new clock domain.zio-simPretty print a [.{io-simPretty print simulation trace.|io-simLike {$ but does not show the result value.}io-simTrace each event using ; this is useful when a trace ends with a pure error, e.g. an assertion.io-simThis instance adds a trace when a variable was written, just after the stm transaction was committed.3Traces the first value using dynamic tracing, like q does, i.e. with  EventDynamic; the string is traced using 2.io-simJust like the IO instance, we don't actually check anything hereio-sim written tvarsio-sim read tvarsio-sim created tvars=io-simstm tx wrote to theseio-simand created theseio-simeffect performed (only for IOSimPOR1) | aborted an STM transaction (by an exception)For IOSimPOR it also holds performed effect.?io-simeffect performed (only for IOSimPOR)Lio-simcurrent threadio-simqueried threadzio-simwidth of the timeio-simwidth of thread idio-simwidth of thread labelpomlknj !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVYWXZ[\]^_`abcdefghiqrstuvwxyz{|}~ Safe-Inferred)*:kio-sim&Unsafe method which removes a timeout.It's not part of public API, and it might cause deadlocks when used in a wrong context.It is defined here rather so that it's not exposed to the user, even tough one could define it oneself.TODO: % constructors should be defined here.  Safe-Inferred'*?IGio-simInternal state.io-simAll threads other than the currently running thread: both running and blocked threads.io-sim current timeio-sim#ordered list of timers and timeoutsio-simtimeout locks in order to synchronize the timeout handler and the main threadio-sim next unused io-sim next unused  | previous steps (which we may race with). Note this is *lazy*, so that we don't compute races we will not reverse.io-sim0control the schedule followed, and initial valueio-simlimit on the computation time allowed per scheduling step, for catching infinite loops etcio-sim.Timers mutable variables. First one supports v api, the second one , the third one .io-simv timer.io-sim registerDelay timer.io-sim threadDelay timer run by  which was assigned the given " (only used to report in a trace).io-simtimeout timer run by  which was assigned the given " (only used to report in a trace).io-sim-Interpret the simulation monotonic time as a  since the start.io-simInsert thread into .io-simSchedule / run a thread.io-simThis function receives a list of TimerTimeout values that represent threads for which the timeout expired and kills the running thread if needed.This function is responsible for the second part of the race condition issue and relates to the s  locking explanation (here is where the assassin threads are launched. So, as explained previously, at this point in code, the timeout expired so we need to interrupt the running thread. If the running thread finished at the same time the timeout expired we have a race condition. To deal with this race condition what we do is look at the lock value. If it is  this means that the running thread already finished (or won the race) so we can safely do nothing. Otherwise, if the lock value is  we need to acquire the lock and launch an assassin thread that is going to interrupt the running one. Note that we should run this interrupting thread in an unmasked state since it might receive a  ThreadKilled exception.io-simIterate through the control stack to find an enclosing exception handler of the right type, or unwind all the way to the top level for the thread.Also return if it's the main thread or a forked thread since we handle the cases differently.io-sim#The most general method of running i is in 6 monad. One can recover failures or the result from U with  traceResult , or access  TraceEvent$s generated by the computation with  traceEvents1. A slightly more convenient way is exposed by  runSimTrace.io-simSpecial case of % supporting only var reads and writesio-simTrace a . It must be called only on s that were new or 'written.io-simFor each TVar written to in a transaction (in order) collect the threads that blocked on each one (in order).Also, for logging purposes, return an association between the threads and the var writes that woke them.io-sim turns a current  into , and updates all .We take care that steps can only race against threads in their concurrent set. When this becomes empty, a step can be retired into the "complete" category, but only if there are some steps racing with it.io-siman earlier stepio-sim a later stepio-sim if we are blocked on STMio-siman earlier stepio-sim a later stepomlk$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVYWXZ[]^_`abcdefghiqrstu Safe-Inferred'*?U io-simInternal state.io-simAll threads other than the currently running thread: both running and blocked threads.io-sim current timeio-sim#ordered list of timers and timeoutsio-simlist of clocksio-sim next unused io-sim next unused io-sim#Timers mutable variables. Supports v api, the second one , the third one .io-simv timer.io-sim registerDelay timer.io-sim threadDelay timer run by  which was assigned the given " (only used to report in a trace).io-simtimeout timer run by  which was assigned the given " (only used to report in a trace).io-sim-Interpret the simulation monotonic time as a  since the start.io-simSchedule / run a thread.io-simThis function receives a list of TimerTimeout values that represent threads for which the timeout expired and kills the running thread if needed.This function is responsible for the second part of the race condition issue and relates to the s  locking explanation (here is where the assassin threads are launched. So, as explained previously, at this point in code, the timeout expired so we need to interrupt the running thread. If the running thread finished at the same time the timeout expired we have a race condition. To deal with this race condition what we do is look at the lock value. If it is  this means that the running thread already finished (or won the race) so we can safely do nothing. Otherwise, if the lock value is  we need to acquire the lock and launch an assassin thread that is going to interrupt the running one. Note that we should run this interrupting thread in an unmasked state since it might receive a  ThreadKilled exception.io-simIterate through the control stack to find an enclosing exception handler of the right type, or unwind all the way to the top level for the thread.Also return if it's the main thread or a forked thread since we handle the cases differently.4Also remove timeouts associated to frames we unwind.io-sim#The most general method of running i is in 6 monad. One can recover failures or the result from U with  , or access 1%s generated by the computation with 1. A slightly more convenient way is exposed by .io-simSpecial case of % supporting only var reads and writesio-simTrace a . It must be called only on s that were new or 'written.io-simFor each TVar written to in a transaction (in order) collect the threads that blocked on each one (in order).Also, for logging purposes, return an association between the threads and the var writes that woke them.pmlk-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVYWXZ[\^_`abcdefghiqrstuz{| Safe-Inferred'cio-sim Simulation terminated a failure.io-sim-The main thread terminated with an exception.io-simThe threads all deadlocked.io-simThe main thread terminated normally but other threads were still alive, and strict shutdown checking was requested. See .io-simAn exception was thrown while evaluation the trace. This could be an internal assertion failure of `io-sim` or an unhandled exception in the simulation.io-simSelect all the traced values matching the expected type. This relies on the sim's dynamic trace facility.For convenience, this throws exceptions for abnormal sim termination.io-simLike + but also captures time of the trace event.io-simLike ; but returns partial trace if an exception is found in it.io-simLike ,` but also captures time of the trace event.io-simGet a trace of 2.For convenience, this throws exceptions for abnormal sim termination.io-simLike + but also captures time of the trace event.io-simLike : but return partial trace if an exception is found in it.io-simLike ,` but also captures time of the trace event.io-sim Print all 2 to the console.For convenience, this throws exceptions for abnormal sim termination.io-sim?@ABCDEFGHIJKLMNOPQRSTUVYWXZ[\]^_`abcdefghiqrstuvwxyz{|}~ih$%&'()*+, !"#~stuUpokjmlnpokjmlnVYWXZ[\]^_`abc123456789:;<=>?@ABCDEFGHIJKLMNOPQRST-./0qr{|z}fgdevwxy !"#$%&'()*+,-./0123456 7 8 8 9 : ; < = = > ? @ A B C D E E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r r s t u v w x y z z { { | } ~      l          $          #                                                                                                                  }    $io-sim-1.2.0.0-6RTAPATlZyuKeuX2phRU2Control.Monad.IOSimData.List.TraceControl.Monad.IOSim.CommonTypesControl.Monad.Class.MonadTest exploreRaces&Control.Monad.IOSimPOR.QuickCheckUtilsControl.Monad.IOSimPOR.TimeoutControl.Monad.IOSimPOR.TypesData.Deque.StrictControl.Monad.IOSim.STMControl.Monad.IOSim.TypestraceM Debug.Trace traceEvents traceResultselectTraceEventsselectTraceEventsDynamicprintTraceEventsSay!Control.Monad.IOSim.InternalTypesControl.Monad.IOSimPOR.Internal!Control.Monad.Class.MonadTimer.SI registerDelay threadDelayControl.Monad.IOSim.Internal runSimTrace ThreadLabelTraceConsNilheadtailfilterlengthtoListfromListppTrace $fShow1Trace $fOrd1Trace $fEq1Trace$fMonadFixTrace$fMonadPlusTrace$fAlternativeTrace$fMonadFailTrace $fMonadTrace$fApplicativeTrace $fMonoidTrace$fSemigroupTrace$fBitraversableTrace$fBifoldableTrace$fBifunctorTrace $fShowTrace $fEqTrace $fOrdTrace$fFunctorTraceExplorationSpecExplorationOptionsexplorationScheduleBoundexplorationBranchingexplorationStepTimelimitexplorationReplay ScheduleModscheduleModTargetscheduleModControlscheduleModInsertionScheduleControlControlDefault ControlAwait ControlFollowLabelled l_labelledl_label SimEventTypeEventSayEventLog EventMask EventThrow EventThrowToEventThrowToBlockedEventThrowToWakeupEventThrowToUnmaskedEventThreadForkedEventThreadFinishedEventThreadUnhandledEventTxCommittedEventTxAbortedEventTxBlocked EventTxWakeupEventUnblockedEventThreadDelayEventThreadDelayFiredEventTimeoutCreatedEventTimeoutFiredEventRegisterDelayCreatedEventRegisterDelayFiredEventTimerCreatedEventTimerUpdatedEventTimerCancelledEventTimerFiredEventThreadStatus EventSimStartEventThreadSleepEventThreadWakeEventDescheduleEventFollowControlEventAwaitControlEventPerformActionEventRescheduleSimTrace SimResult MainReturn MainExceptionDeadlockLoopSimEvent SimPOREvent SimRacesFoundseTime seThreadId seThreadLabelseTypeseStepEventlogMarker EventlogEventSTMSimIOSim TraceLoop TraceDeadlockTraceMainExceptionTraceMainReturnTraceRacesFound SimPORTracetraceSTMliftSTsetCurrentTime unshareClock newTimeout readTimeout cancelTimeout awaitTimeout ppSimEventppTrace_ppDebugstdExplorationOptionswithScheduleBound withBranchingwithStepTimelimit withReplay runSimTraceSTFailureFailureExceptionFailureDeadlockFailureSloppyShutdownFailureEvaluationselectTraceEvents'selectTraceRaces selectTraceEventsDynamicWithTimeselectTraceEventsDynamic'!selectTraceEventsDynamicWithTime'selectTraceEventsSayselectTraceEventsSayWithTimeselectTraceEventsSay'selectTraceEventsSayWithTime'traceSelectTraceEventstraceSelectTraceEventsDynamictraceSelectTraceEventsSayrunSim runSimOrThrowrunSimStrictShutdownppEventsexploreSimTracecontrolSimTrace$fExceptionFailure $fShowFailuretvarId tvarLabel tvarCurrenttvarUndo tvarBlocked tvarVClock tvarTraceThreadId RacyThreadId BlockedReason BlockedOnSTMBlockedOnOther ThreadStatus ThreadDone ThreadRunning ThreadBlocked DescheduleSleep TerminatedBlocked InterruptableYieldSomeTVarTVar TVarLabel VectorClockgetVectorClockClockId TimeoutIdTVarId childThreadId setRacyThread unTimeoutId|&&|TestableNoCatchpropertyNoCatch conjoinParconjoinNoCatchconjoinSpeculate.&&| againNoCatchTimeouttimeout unsafeTimeout $fShowTimeoutEffect effectWakeup effectThrows effectForks effectWrites effectReads readEffects writeEffects forkEffect throwToEffect wakeupEffects someTvarIdonlyReadEffect racingEffectsDequesnocuncons MVarDefault)io-classes-1.2.0.0-HaMcVajpS0IC0EbW736pbN%Control.Monad.Class.MonadSTM.InternalSTMputMVarDefaulttakeMVarDefault MVarStateMVarreadMVarDefaultMVarFull MVarEmptyTBQueueDefaultTBQueue TQueueDefaultTQueuelabelTQueueDefaulttraceTQueueDefaultnewTQueueDefaultwriteTQueueDefaultreadTQueueDefaulttryReadTQueueDefaultisEmptyTQueueDefaultpeekTQueueDefaulttryPeekTQueueDefaultflushTQueueDefaultunGetTQueueDefaultlabelTBQueueDefaulttraceTBQueueDefaultnewTBQueueDefaultreadTBQueueDefaulttryReadTBQueueDefaultpeekTBQueueDefaulttryPeekTBQueueDefaultwriteTBQueueDefaultisEmptyTBQueueDefaultisFullTBQueueDefaultlengthTBQueueDefaultflushTBQueueDefaultunGetTBQueueDefaultnewEmptyMVarDefaultnewMVarDefaulttryPutMVarDefaulttryTakeMVarDefaulttryReadMVarDefaultisEmptyMVarDefaultbase GHC.MaybeNothingStepIdAtomicallyFrame atomically BranchFrame BranchStmAOrElse OrElseStmA CatchStmACatchStmControl.Monad.Class.MonadThrowcatchNoOpStmA StmTxResultStmTxCommitted traceTVar StmTxBlocked StmTxAbortedControl.Monad.Class.MonadFork labelThread labelTVarControl.Monad.Class.MonadSaysaythrowToretryControl.Monad.Class.MonadTimer System.IOputStrLnghc-prim GHC.TypesIONegativeTimeoutData.Typeable.InternalTypeableGHC.STSTControl.Monad.Class.MonadSTMonadSTtrace$fMonadTraceSTMIOSim$fNoThunksIOSim(si-timers-1.2.0.0-H742V7aelw2JeyE6Axabs9 Control.Monad.Class.MonadTime.SIaddTimediffTimeTimeStmStackTimeoutExceptionStmA OutputStm ReturnStmThrowStmNewTVar LabelTVarReadTVar WriteTVarRetrySayStm TraceTVar LiftSTStmFixStmunSTMSimACatch CancelTimeout NewTimeoutFixReturnOutputSayLiftST GetMonoTime GetWallTime SetWallTime UnshareClock StartTimeoutUnregisterTimeout RegisterDelay ThreadDelayThrowEvaluateFork GetThreadId LabelThread AtomicallyThrowTo SetMaskState GetMaskStateYieldSim ExploreRacesThrower ThrowSelf ThrowOtherunIOSimrunIOSimrunSTM execReadTVarunsafeUnregisterTimeoutIsLocked NotLockedLocked ControlStack MainFrame ForkFrame MaskFrame CatchFrame TimeoutFrame DelayFrame ThreadControlSimStatethreadscurTimetimersclocksnextVidnextTmidcontrolperStepTimeLimitTimerCompletionInfoTimerTimerRegisterDelayTimerThreadDelay TimerTimeouttimeSinceEpoch time-1.11.1.1(Data.Time.Clock.Internal.NominalDiffTimeNominalDiffTime insertThreadrunqueuescheduleforkTimeoutInterruptThreadsunwindControlStackControl.Monad.ST.Lazy.ImpexecAtomically'execAtomically traceTVarSTthreadsUnblockedByWrites updateRacesStepStepInfo activeRaceshappensBeforeStepunblockThreadsTrue racingStepscontrolSimTraceSTreplaySimTrace