kansas-lava-cores-0.1.2.1: FPGA Cores Written in Kansas Lava.

Safe HaskellNone
LanguageHaskell2010

Hardware.KansasLava.FIFO

Synopsis

Documentation

resetable :: forall a c. (Clock c, Rep a) => Signal c Bool -> a -> Signal c a -> Signal c a Source

Make a sequence obey the given reset signal, returning given value on a reset.

fifoFE Source

Arguments

:: (Size counter, Size ix, counter ~ ADD ix X1, Rep a, Rep counter, Rep ix, Num counter, Num ix, Clock c, sig ~ Signal c) 
=> Witness ix

depth of FIFO

-> Signal c Bool

hard reset option

-> Patch (sig (Enabled a)) (sig (Enabled (ix, a)) :> sig Bool) (sig Ack) (sig Ready :> sig counter)

input, and Seq trigger of how much to decrement the counter, ^ backedge for input, internal counter, and write request for memory.

fifoBE Source

Arguments

:: (Size counter, Size ix, counter ~ ADD ix X1, Rep a, Rep counter, Rep ix, Num counter, Num ix, Clock c, sig ~ Signal c) 
=> Witness ix 
-> Signal c Bool

reset -> (Signal comb Bool -> Signal comb counter -> Signal comb counter) -> Seq (counter -> counter)

-> Patch (sig (Enabled a) :> sig counter) (sig (Enabled a)) (sig (Enabled ix) :> sig Bool) (sig Ack) 

fifoMem :: forall a c1 c2 counter ix sig1 sig2. (Size counter, Size ix, counter ~ ADD ix X1, Rep a, Rep counter, Rep ix, Num counter, Num ix, Clock c1, Clock c2, sig1 ~ Signal c1, sig2 ~ Signal c2, c1 ~ c2) => Witness ix -> Patch (sig1 (Enabled (ix, a)) :> sig1 Bool) (sig2 (Enabled a) :> sig2 counter) (sig1 Ready :> sig1 counter) (sig2 (Enabled ix) :> sig2 Bool) Source

fifoCounter :: forall counter. (Num counter, Rep counter) => Seq Bool -> Seq Bool -> Seq Bool -> Seq counter Source

fifoCounter' :: forall counter. (Num counter, Rep counter) => Seq Bool -> Seq counter -> Seq counter -> Seq counter Source

fifo :: forall a c counter ix. (Size counter, Size ix, counter ~ ADD ix X1, Rep a, Rep counter, Rep ix, Num counter, Num ix, Clock c) => Witness ix -> Signal c Bool -> Patch (Signal c (Enabled a)) (Signal c (Enabled a)) (Signal c Ack) (Signal c Ack) Source

mulBy :: forall x sz c. (Clock c, Size sz, Num sz, Num x, Rep x) => Witness sz -> Signal c Bool -> Signal c x Source

divBy :: forall x sz c. (Clock c, Size sz, Num sz, Rep sz, Num x, Rep x) => Witness sz -> Signal c Bool -> Signal c Bool -> Signal c x Source