lion: RISC-V Core
Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT FPGA development board and is written in Haskell using Clash.
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- lion-0.4.0.1.tar.gz [browse] (Cabal source package)
- Package description (as included in the package)
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Versions [RSS] | 0.1.0.0, 0.2.0.0, 0.3.0.0, 0.4.0.0, 0.4.0.1 |
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Change log | CHANGELOG.md |
Dependencies | base (>=4.13 && <4.21), clash-prelude (>=1.2.5 && <1.9), generic-monoid (>=0.1 && <0.2), ghc-typelits-extra, ghc-typelits-knownnat, ghc-typelits-natnormalise, ice40-prim (>=0.3 && <0.3.1.5), lens (>=4.19 && <5.4), mtl (>=2.2 && <2.4) [details] |
License | BSD-3-Clause |
Copyright | (c) 2021-2024 David Cox |
Author | dopamane <standard.semiconductor@gmail.com> |
Maintainer | dopamane <standard.semiconductor@gmail.com> |
Category | Hardware |
Bug tracker | https://github.com/standardsemiconductor/lion/issues |
Source repo | head: git clone https://github.com/standardsemiconductor/lion |
Uploaded | by dopamane at 2024-08-03T07:54:16Z |
Distributions | |
Downloads | 517 total (9 in the last 30 days) |
Rating | 2.0 (votes: 1) [estimated by Bayesian average] |
Your Rating | |
Status | Docs uploaded by user [build log] All reported builds failed as of 2024-08-03 [all 2 reports] |