úÎcQ]k      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghij!non-portable (DeriveDataTypeable) experimentalpweaver@signalicorp.com_Binary operators. ?These operators include almost all VHDL and Verilog operators. N precedence and pretty-printing are language specific, and defined elsewhere. : exponentation operators were introduced in Verilog-2001.  some operators are not prefix/-infix, such as verilog concatenation and the  conditional ( x ? y : z,) operator. those operators are defined in  8.  VHDL has both "logical" and " barithmetic" shift operators, which we  don' t yet distinguish between here.  VHDL has both a mod and a rem% operator, but so far we only define  .  VHDL has a concat operator (& ) that isn't yet supported here. Use  = instead.  VHDL has an abs operator that isn't yet supported here.  Unary operators % is logical negation, $ is bitwise negation. #, ",  !,  , , and  are sometimes called " reduction  operators".  !"#$%&'(An (: is something that can appear on the left-hand side of an  assignment. We'<re lazy and do not enforce any restriction, and define this  simply to be 8. ) Behavioral sequential statement *0a function call that can appear as a statement, 3 useful for calling Verilog tasks (e.g. $readmem). + multiple statements in sequence ,+case statement, with optional default case -if statement .non-blocking assignment /0123456Aa single bit. in vhdl, bits are different than 1-bit bitvectors 7 a number 87Expr is a combination of VHDL and Verilog expressions. IIn VHDL, concatenation is a binary operator, but in Verilog it takes any L number of arguments. In this AST, we define it like the Verilog operator. M If we translate to VHDL, we have to convert it to the VHDL binary operator. (There are some HDL operators that we don'#t represent here. For example, in J Verilog there is a multiple concatenation (a.k.a. replication) operator,  which we don't bother to support. 9a function application :!application of a binary operator ; application of a unary operator <conditional expression =concatenation >,case expression. supports multiple matches 1 per result value, and an optional default value ? x[e : e+i], where i can be negative @  x[e1 : e2]A x[e]B(a quoted string (useful for parameters) Ca variable ference Da sized or unsized literal E.An event can be triggered by the rising edge (G) or falling edge  (F) of a signal. FGHIJFA constant expression is simply an expression that must be a constant L (i.e. the only free variables are static parameters). This restriction is  not made in the AST. KA LK> tells us the type of a bit vector. It can count up or down. LMA declaration, analogous to an "item" in the Verilog formal syntax. N@A basic comment (typically is placed above a decl of interest). > Newlines are allowed, and generate new single line comments. O?A statement that executes once at the beginning of simulation.  Equivalent to Verilog "initial" statement. PCA sequential process with clock and (optional) asynchronous reset. QA module/Aentity instantiation. The arguments are the name of the module, E the name of the instance, the parameter assignments, the input port / connections, and the output port connections. R5These are permanent assignments to memory locations,  of the form mem[addr] = val SA mem (reg3 in Verilog) is stateful. It can be assigned by a 1 non-blocking assignment (or blocking, but we don't support those yet) 9 within a process. TODO: support optional initial value 3The first range is the most significant dimension.  So, MemDecl x (0, 31) (7, 0)* corresponds to the following in Verilog:  reg [7:0] x [0:31] TUA net (wire= in Verilog) has a continuously assigned value. The net can , be declared and assigned at the same time ( Just Expr), or separately  (Nothing) in a  NetAssign. VThe size of a wire. WAn identifier name. XA Module corresponds to a "module" in Verilog or an "entity" in VHDL. YZ[\]^_  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_XYZ[\]^WVMUTSRQPONKLJHIEGF8DCBA@?>=<;:94765/3210).-,+*('&%$#"!  _   '&%$#"!  !"#$%&'().-,+**+,-./3210012347655678 DCBA@?>=<;:99:;<=>?@ABCDEGFFGHIIJKLLMUTSRQPONNOPQRSTUVWXYZ[\]^YZ[\]^ non-portable experimentalpweaver@signalicorp.com _DProduce a new module in which some variables have been inlined. An  expression is inlined (and it'.s declaration removed) if it only used in one  place in the entire module. klmnopqr___ non-portable experimentalpweaver@signalicorp.com `abcdefg-Given a direction and size, maybe generate a LK, where a size of 1  yields s. hHConcatenate a list of expressions, unless there is just one expression. iMake a +? statement from a list of statements, unless there is just one  statement. jNgenerate a process declaration for a generic register based on the following: & the register name (as an expression)  clock expression  width of the register / optional asynchronous reset and initial value  optional clock enable 0 optional synchronous restart and initial value  optional load enable : when enabled, the expression to assign to the identifier IYou can implement a shift register by passing in a concatenation for the M register expression and the input expression, though that is not compatible  with VHDL. `abcdefghij `bacdefghij `baabcdefghij non-portable experimentalpweaver@signalicorp.comtuvwxytuvwxytuvwxyz      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGH9IJKLLMNNOPQRSTUVWXYZZ[\]^_`abcdefghijklmnopqrstuvwxyz{|} netlist-0.3.1Language.Netlist.ASTLanguage.Netlist.InlineLanguage.Netlist.UtilLanguage.Netlist.ExamplesBinaryOpShiftRightArithShiftLeftArith RotateRight RotateLeft ShiftRight ShiftLeftXnorXorNorOrNandAnd GreaterEqual GreaterThan LessEqualLessThanLOrLAnd CNotEqualsCEquals NotEqualsEqualsModuloDivideTimesMinusPlusPowUnaryOpUXnorUXorUNorUOrUNandUAndNegLNegUMinusUPlusLValueStmt FunCallStmtSeqCaseIfAssignBitZUFTExprLit ExprBitVectorExprBitExprNumExpr ExprFunCall ExprBinary ExprUnaryExprCond ExprConcatExprCase ExprSliceOff ExprSlice ExprIndex ExprStringExprVarEdgeNegEdgePosEdgeEvent ConstExprRangeDecl CommentDeclInitProcessDecl ProcessDeclInstDecl MemAssignMemDecl NetAssignNetDeclSizeIdentModule module_name module_inputsmodule_outputsmodule_statics module_decls inlineModule DirectionDownUpunsizedIntegerunsizedIntegral sizedInteger sizedIntegral makeRange exprConcat statements generateReg replaceExprs removeDecls getBindingsgetDeclBinding shouldInline getIdentExprsgetAllmaybeExprIdentbase Data.MaybeNothingtds var_exprsstmtsif0if1