+      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  Safe-Inferredthe cpu configuration typeboot(start) pc instruction memory start addressinstruction memory sizedata memory start addressdata memory sizethe default configuration&You can change the configuration here. Safe-Inferred"the Flag conditions  greater equal  greater than  little equal  little than  not equalequalthe general purpose registers.(You can create registers as you like :-)the instruction definition.+You can create instructions as you like :-)POperand order is Intel, ARM, MIPS, PowerPC,... order. (opcode dst src1 src2) undefinedmemory(GReg) <- GRegGReg <- memory(GReg)goto R0/goto GReg; R0 <- PC // absolute addressing%goto GReg // absolute addressing.goto (PC + Int) // pc relative addressing ?if (FCond(Flag)) goto (PC + Int) // pc relative addressing!%GReg <- GReg << GReg // logical shift"GReg <- GReg ^ GReg# GReg <- ~GReg$GReg <- GReg | GReg%GReg <- GReg & GReg&GReg <- GReg / GReg'GReg <- GReg * GReg((GReg <- GReg << GReg // arithmetic shift)GReg <- abs(GReg)*Flag <- compare(GReg, GReg)+GReg <- GReg - GReg,GReg <- GReg + GReg- GReg <- PC. GReg <- GReg/ GReg <- Int0halt (stop the processor)1 no operation+  !"#$%&'()*+,-./01*  !"#$%&'()*+,-./01*10/.-,+*)('&%$#"!   10/.-,+*)('&%$#"!  Safe-Inferred2the data memory array3the data memory image ' [(StartAddress, [Data1, Data2, ...])]Example:  [(0, [1, 5, 7, 0x20])]6the instruction memory array7the instruction memory image 5 [(StartAddress, [Instruction1, Instruction2, ...])]Example: % [(0, [MOVI R1 0, LD R0 R1, HALT])]9!initialize the instruction memory:preset the instruction memory;modify the instruction memory<0fetch an instruction from the instruction memory=get an instruction memory image>0extract instructions from the instruction memory?initialize the data memory@preset the data memoryAget a data from the data memoryBmodify the data memoryC modify the data memory by valuesDget a data memory imageE(extract data values from the data memory23456789:;<=>?@ABCDE23456789:;<=>?@ABCDE73628549:;<=>?@ABCDE23456789:;<=>?@ABCDE Safe-Inferred H carry flagI zero flagK.initialize the general purpose registers arrayL,get a value of the general purpose registerM/get values of the general purpose register pairN/get all values of the general purpose registersO modify general purpose registersP#initialize the flag registers arrayQ&get a value of the flag register valueR$get all values of the flag registersSmodify flag registersTjudge a flag conditionFGHIJKLMNOPQRSTFGHIJKLMNOPQRSTJGIHFKLMNOPQRST FGIHJKLMNOPQRST Safe-InferredU(the cpu state (processor internal state)This is the result type from   function.get each values by \, ], ^, _, `, aVthe result stateWexecution errorXdebugger triggeredYcpu halt(stop)Z normal result[the cpu eval monad\ 5 > pcFromCpuState $ run [(0,[MOVI R0 7, HALT])] [] 1] E > grFromCpuState $ run [(0,[MOVI R0 7, HALT])] [] [7,0,0,0,0,0,0,0]^ A > flFromCpuState $ run [(0,[MOVI R0 7, HALT])] [] [False,False]_ \ > imemFromCpuState $ run [(0,[MOVI R0 7, HALT])] [] [(0,[MOVI R0 7,HALT,UNDEF,UNDEF,...])]` b > dmemFromCpuState $ run [(0,[MOVI R0 0, MOVI R1 10, ST R0 R1, HALT])] [] [(0,[10,0,0,0,0,...])]a*dump Cpu state (without instruction image)  > putStr $ dumpCpuState $ run [(0,[MOVI R0 7, HALT])] [] pc : 1 gr : [7,0,0,0,0,0,0,0] fl : [False,False] dm : [(0,[7,0,0,0,0,...])]ba default CpuStatec*initialize CpuState by inst and data imaged read the pce update the pcExample: d jumpRI :: Int -> EvalCpu ResultStat jumpRI ad = do pc <- readPc updatePc (pc + ad)fincrement the pcgread a general purpose registerExample: ` jump :: GReg -> EvalCpu ResultStat jump reg = do ad <- readGReg reg updatePc adh"read general purpose register pairi!update a general purpose registerExample: c movpc :: GReg -> EvalCpu ResultStat movpc reg = do pc <- readPc updateGReg reg pcjread flag registersExample:  branchRI :: FCond -> Int -> EvalCpu ResultStat branchRI fcond ad = do flags <- readFlags if judgeFCond flags fcond then jumpRI ad else incPck update a flagExample:  cmpRR :: GReg -> GReg -> EvalCpu ResultStat cmpRR ra rb = do (ra', rb') <- readGReg2 ra rb updateFlag FLZ (ra' == rb') updateFlag FLC (ra' < rb')l0fetch an instruction from the instruction memorym&read a data value from the data memoryExample:  load :: GReg -> GReg -> EvalCpu ResultStat load ra rb = do rb' <- readGReg rb ra' <- readDmem rb' updateGReg ra ra'nupdate the data memoryExample:  store :: GReg -> GReg -> EvalCpu ResultStat store ra rb = do (ra', rb') <- readGReg2 ra rb updateDmem ra' rb' "UVWXYZ[\]^_`abcdefghijklmnUVWXYZ[\]^_`abcdefghijklmn[U\]^_`abcVZYXWdefghijklmnUVZYXW[\]^_`abcdefghijklmn Safe-Inferredorun the processorExample: simple run ] > run [(0, [MOVI R0 20, HALT])] [] pc : 1 gr : [20,0,0,0,0,0,0,0] fl : [False,False] ...Example: run with initial data p > run [(0, [MOVI R1 0, LD R0 R1, HALT])] [(0,[100])] pc : 2 gr : [100,0,0,0,0,0,0,0] fl : [False,False] ...pevaluate a program u run :: InstImage -> DataImage -> CpuState run insts vals = execState (evalProg False) (initCpuStateMem insts vals)opopopopNoneq)parse instructions from a ByteString dataExample: ; > parseInst (B.pack "mov r0,1\n halt\n") [MOVI R0 1,HALT]rparse instructions from a fileExample: 7 > parseInstFile "examples/test0.asm" [MOVI R0 1,HALT]:qrqrqr:qr Safe-Inferredsbreak operatorst greater equalu greater thanv little equalw little thanx not equalyequalzbreak conditionsExample:  BrkPc BEQ 3 -- pc == 3 BrkPc BGE 0x80 -- pc >= 0x80 BrkGReg R0 BEQ 7 -- R0 == 7 BrkDmem 0x20 BLT 4 -- *0x20 < 4{data memory break|register break}pc break~always one step breakno breaktrace conditions for  or trace memory storetrace memory loadtrace branch informationtrace call target addresstrace pctrace registerstrace instructionsdata type for  log debugging run7Example: run with a break condition. (break at pc == 1) v > runDbg [] [(BrkPc BEQ 1)] [(0,[MOVI R0 7, MOVI R1 8, HALT])] [] pc : 1 gr : [7,0,0,0,0,0,0,0] fl : [False,False]3Example: run with trace output. (instruction trace)  > runDbg [TrcInst] [] [(0,[MOVI R0 7, MOVI R1 8, HALT])] [] TrcInst: pc : 0 MOVI R0 7 TrcInst: pc : 1 MOVI R1 8 TrcInst: pc : 2 HALTdebugging run for IO output3Example: run with trace output. (instruction trace)  > runDbgIO [TrcInst] [] [(0,[MOVI R0 7, MOVI R1 8, HALT])] [] TrcInst: pc : 0 MOVI R0 7 TrcInst: pc : 1 MOVI R1 8 TrcInst: pc : 2 HALT1stuvwxyz{|}~stuvwxyz{|}~z~}|{syxwvutsyxwvutz~}|{  Safe-Inferred the profile mode for ,  and memory store profilememory load profilebranch, jump, call profile call profile pc profileinstruction profilerun the profiler"Example: instruction count profile  > runProf [ProfInst] [(0,[MOVI R1 0, MOVI R2 8, ST R1 R2, HALT])] [] instruction profile: MOVI 2 HALT 1 ST 1 total 4Example: memory store profile  > runProf [ProfStore] [(0,insts)] [] Memory store address profile: address count 0x00000000 1 0x00000001 1 0x00000002 1 0x00000003 1 0x00000004 1 0x00000005 1 0x00000006 1 total 7!Example: branch,jump,call profile  > runProf [ProfBranch] [(0,insts)] [] Branch/Jump/Call target profile: address count 0x00000007 6 total 6 Branch/Jump/Call direction profile: T/N count Taken 6 Not 1 total 7run the profiler for IO outputExample: > runProfIO [ProfInst] [(0,[MOVI R1 0, MOVI R2 8, ST R1 R2, HALT])] [] instruction profile: MOVI 2 HALT 1 ST 1 total 4profile functionExample: > prof [ProfInst] $ fst $ runDbg [TrcInst] [] [(0,insts)] [] instruction profile: MOVI 2 HALT 1 ST 1 total 4            Noneinteractive debugger driver.Example:  > runIdbIO [TrcInst] [] [(0,insts)] [] For help, type "help". (idb) info reg pc : 0 gr : [0,0,0,0,0,0,0,0] fl : [False,False] (idb) s TrcInst: pc : 0 MOVI R0 0 (idb) s TrcInst: pc : 1 MOVI R1 1 (idb) b 4 Num Enb What 1 y pc == 4 (idb) c TrcInst: pc : 2 MOVI R2 2 TrcInst: pc : 3 MOVI R3 3 (idb) x/10 0 0x00000000: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000004: 0x00000000 0x00000000 0x00000000 0x00000000 0x00000008: 0x00000000 0x00000000 (idb) qplease see "help" commandO !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdef<-,+*)('&%$#"! ./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdef None%qrstuvwxyz{|}~%qrz~}|{syxwvut  Safe-Inferred4  !"#$%&'()*+,-./0137U\]^_`ao4o10/.-,+*)('&%$#"!  73U\]^_`ag !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{ |}~        b                        ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k lprocessor-creative-kit-0.1.0.1Language.Pck.Cpu.ConfigLanguage.Pck.Cpu.InstructionLanguage.Pck.Cpu.MemoryLanguage.Pck.Cpu.RegisterLanguage.Pck.Cpu.StateLanguage.Pck.Cpu.ExecutionLanguage.Pck.Tool.AssemblerLanguage.Pck.Tool.DebuggerLanguage.Pck.Tool.Profiler%Language.Pck.Tool.InteractiveDebuggerLanguage.Pck.CpurunLanguage.Pck.Tool CpuConfig cfgStartPc cfgImemStart cfgImemSize cfgDmemStart cfgDmemSize cpuConfigFCondFCGEFCGTFCLEFCLTFCNEFCEQGRegR7R6R5R4R3R2R1R0InstUNDEFSTLDRETCALLJJRIBRILSHXORNOTORANDDIVMULASHABSCMPSUBADDMOVPCMOVMOVIHALTNOP DmemArray DataImageDValueDAddress ImemArray InstImageIAddressinitImem presetImem modifyImems fetchImem getInstImage extractImemsinitDmem presetDmemgetDmem modifyDmem modifyDmems getDataImage extractDmems FlagArrayFlagFLCFLZ GRegArrayinitGReggetGReggetGReg2getGRegs modifyGReginitFlaggetFlaggetFlags modifyFlag judgeFCondCpuState ResultStatRsErrRsDbgBrkRsHaltRsNormalEvalCpupcFromCpuStategrFromCpuStateflFromCpuStateimemFromCpuStatedmemFromCpuState dumpCpuState initCpuStateinitCpuStateMemreadPcupdatePcincPcreadGReg readGReg2 updateGReg readFlags updateFlag fetchInstreadDmem updateDmemevalProg parseInst parseInstFileDbgOrdBGEBGTBLEBLTBNEBEQDbgBrkBrkDmemBrkGRegBrkPcBrkOneBrkNonDbgTrcTrcStoreTrcLoad TrcBranchTrcCallTrcPcTrcRegTrcInstTrcLogrunDbgrunDbgIO evalProgDbgProfMode ProfStoreProfLoad ProfBranchProfCallProfPCProfInstrunProf runProfIOprofrunIdbIO $fNFDataInstimemSizeimemMinimemMaxdmemSizedmemMindmemMaxstate_pcstate_grstate_fl state_imem state_dmem showCpuState$fShowCpuStateevalStepjumpRIjumpbranchRIlinkRegcallretmovimmmovpcloadstorecmpRRbiopInst uniopInst logicalShiftF3F2F1F0 ParseInstfileinstLineinst miscInstsmovInsts arithInsts logicInsts jumpInstsmemInstsinst0inst1inst2inst3 strGRegPrefgregpcfcond strImmPrefimm immNoSignimmMinusimmHex strMemBeg strMemEndmem gregNames strToGReg strToFCond skipSpaces delimSpace delimComma strCmntLinestrCmntRangeBegstrCmntRangeEnd lineComment rangeComment skipElements skipEmptyLineskipLineCommentskipRangeCommentparseInstAnalyze parseEachLineextractNonEmptyLineisNonEmptyLineremoveComments commentParse normalLinelineCommentEolrangeCommentEol extractEol dbgRunLimit checkRunLimittracePre tracePost traceManytraceOnetracePc traceInsttraceReg traceLoad traceStore traceCall traceAddress isLoadInst isStoreInst isCallInst traceBranchpprHex pprHexList pprSIIInst pprTrcBranch checkBreakbreakOneordFunc KeyCounts modeProfToTrcprofOne pprInstCounts pprLoadCountspprStoreCounts pprCallCountspprBranchAdCountspprBranchTNCounts initKeyCountsaddKey calcKeyCounts pprTrcCounts calcTrcCounts extractLines extractField filterLinesfstHextoHexBSpairMapParseCmdCmdCBlank CWatchDmem CWatchGRegCWatchPcCBCDisableCEnableCDeleteCPwCXCDisasCrCDisasAdCInfoBCInfoRegCSCCCRunCHelpCQuitBrkTable printUsage printUnknown printRegs printDisasmCr printDisasmAd printDisasmpprInst printDmempprDmemppr0x08xsetDmem setBrkTablegetEnableBrkTable printBrkTable pprBrkTable showDbgBrk showDbgOrd addBrkTabledeleteBrkTableenableBrkTabledisableBrkTablesetFstNlinecommandcmdBlankcmdQuitcmdHelpcmdRuncmdScmdC cmdInfoRegcmdInfoB cmdDisasAd cmdDisasCrcmdXncmdX1cmdPrcmdPw cmdDelete cmdEnable cmdDisablecmdB cmdWatchPc cmdWatchGReg cmdWatchDmemnum numNoSignnumMinusnumHexdbgord strToDbgOrd