Hardware.SiClock
type Frequency
type Divider
data Config
defaultConfig
defaultConfigEnv
testIO
type Synth a
runSynth
runSynthWith
askXtalFrequency
askMaxPLLFrequency
data PLL
data CLK
pllReset
clk0_On
clk0_Off
data DividerPair
setDividers
defaultDividers
setPLLDivider
setPLLDivider_A
setPLLDivider_B
setCLKDivider
data CLK_Control_bits
setCLKControl
setCLKControlRaw
controlBitsToWord8
data DividerConf
toDividerConf
setDividerRaw
class DividerAddr a
_SI_CLK0_CONTROL
_SI_CLK1_CONTROL
_SI_CLK2_CONTROL
_SI_SYNTH_PLL_A
_SI_SYNTH_PLL_B
_SI_PLL_RESET
_SI_CLOCK_I2C_DEVICE
_SI_CLOCK_I2C_ADDRESS
_SI_CLOCK_XTAL_FREQUENCY
_SI_CLOCK_MAX_PLL_FREQUENCY