verilog: A Verilog parser.

[ bsd3, embedded, hardware, language, library ] [ Propose Tags ] [ Report a vulnerability ]

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Modules

[Last Documentation]

Language
- Language.Verilog
  - Language.Verilog.Lexer
  - Language.Verilog.Parser
  - Language.Verilog.Preprocessor
  - Language.Verilog.Tokens

Downloads

verilog-0.0.0.tar.gz [browse] (Cabal source package)
Package description (as included in the package)

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Package maintainers

TomHawkins

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Versions [RSS]	0.0.0, 0.0.1, 0.0.2, 0.0.4, 0.0.5, 0.0.6, 0.0.7, 0.0.8, 0.0.9, 0.0.10, 0.0.11
Dependencies	array (>=0.3.0.0 && <0.4), base (>=4.0 && <5), containers (>=0.3.0.0 && <0.4), mtl (>=1.1.0.1 && <2.1), parsec (>=2.1.0.1 && <2.2) [details]
License	BSD-3-Clause
Author	Tom Hawkins <tomahawkins@gmail.com>
Maintainer	Tom Hawkins <tomahawkins@gmail.com>
Category	Language, Hardware
Home page	http://github.com/tomahawkins/verilog
Source repo	head: git clone git://github.com/tomahawkins/verilog.git
Uploaded	by TomHawkins at 2011-07-18T04:17:47Z
Distributions
Reverse Dependencies	1 direct, 0 indirect [details]
Downloads	7899 total (12 in the last 30 days)
Rating	(no votes yet) [estimated by Bayesian average]
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Status	Docs not available [build log] All reported builds failed as of 2016-12-27 [all 7 reports]