verilog: A Verilog parser.

[ bsd3, embedded, hardware, language, library ] [ Propose Tags ]

TODO

Versions [faq] 0.0.0, 0.0.1, 0.0.2, 0.0.4, 0.0.5, 0.0.6, 0.0.7, 0.0.8, 0.0.9, 0.0.10, 0.0.11
Dependencies array (>=0.3.0.0 && <0.4), base (>=4.0 && <5), containers (>=0.3.0.0 && <0.4), mtl (>=1.1.0.1 && <2.1), parsec (>=2.1.0.1 && <2.2) [details]
License BSD-3-Clause
Author Tom Hawkins <tomahawkins@gmail.com>
Maintainer Tom Hawkins <tomahawkins@gmail.com>
Category Language, Hardware
Home page http://github.com/tomahawkins/verilog
Source repo head: git clone git://github.com/tomahawkins/verilog.git
Uploaded by TomHawkins at Mon Jul 18 04:17:47 UTC 2011
Distributions NixOS:0.0.11
Downloads 4334 total (98 in the last 30 days)
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Status Hackage Matrix CI
Docs not available [build log]
All reported builds failed as of 2016-12-27 [all 7 reports]

Modules

  • Language
    • Language.Verilog
      • Language.Verilog.Lexer
      • Language.Verilog.Parser
      • Language.Verilog.Preprocessor
      • Language.Verilog.Tokens

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