name:    verilog
version: 0.0.2

category: Language, Hardware

synopsis: A Verilog parser.

description:
  This parser supports a very small subset of Verilog-95.
  It is intended primarly for machine generated, synthesizable code.

author:     Tom Hawkins <tomahawkins@gmail.com>
maintainer: Tom Hawkins <tomahawkins@gmail.com>

license:      BSD3
license-file: LICENSE

homepage: http://github.com/tomahawkins/verilog

build-type:    Simple
cabal-version: >= 1.6

library
    build-depends:
        base       >= 4.0     && < 5,
        array,
        polyparse

    exposed-modules:
        Language.Verilog
        Language.Verilog.Tokens
        Language.Verilog.Types
        Language.Verilog.Lex
        Language.Verilog.Parse
        Language.Verilog.Preprocess

    extensions:

    ghc-options: -W

source-repository head
    type:     git
    location: git://github.com/tomahawkins/verilog.git