name:    verilog
version: 0.0.8

category: Language, Hardware, Embedded

synopsis: Verilog parser and DSL.

description:
  A parser and DSL supporting a small subset of Verilog-95.
  Intended for machine generated, synthesizable code.

author:     Tom Hawkins <tomahawkins@gmail.com>
maintainer: Tom Hawkins <tomahawkins@gmail.com>

license:      BSD3
license-file: LICENSE

homepage: http://github.com/tomahawkins/verilog

build-type:    Simple
cabal-version: >= 1.8

library
  build-tools:
    alex  >= 3 && < 4,
    happy >= 1 && < 2
  build-depends:
    base       >= 4.0   && < 5.0,
    array      >= 0.4   && < 5.0,
    monadLib   >= 3.7   && < 4.0

  exposed-modules:
    Data.BitVec
    Language.Verilog
    Language.Verilog.AST
    Language.Verilog.DSL
    Language.Verilog.Parser
    Language.Verilog.Parser.Lex
    Language.Verilog.Parser.Parse
    Language.Verilog.Parser.Preprocess
    Language.Verilog.Parser.Tokens

  extensions:

  ghc-options: -W -fprof-auto

source-repository head
  type:     git
  location: git://github.com/tomahawkins/verilog.git