!ky      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./012345678 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~                               !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopq r!s!t!u!v!w!x!y!z!{!|!}!~!!!!!!!!!!!!!!!!!"""""""""""""""""""""""""""#####&$SafeJ9"Base types for the circuit module.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNoneP verismithENewtype for a named edge which is empty, as it does not need a label. verismith<Newtype for a node in the circuit, which is an 'LNode Gate'. verismith:Newtype for the Circuit which implements a Graph from fgl.  verismithThe types for all the gates.   Internal helpers for generation.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNoneY verismith Convert an integer into a label. fromNode 5"w5" verismithGeneral function which runs  over a graph. verismith#Takes two functions that return an S, and compares there results to 0 and not 0 respectively. This result is returned. verismith`Returns all the input nodes to a graph, which means nodes that do not have an input themselves. verismith8Returns all the output nodes to a graph, similar to the  function.Random generation for DAG(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNonea verismithRemove duplicates. verismithRemove duplicates. verismithJGen instance to create an arbitrary edge, where the edges are limited by n that is passed to it. verismith&Gen instance for a random acyclic DAG. verismith2Generate a random acyclic DAG with an IO instance. verismithQThe generated graph. It uses Arbitrary to generate random instances of each node2Counter example parser to load the counter example(c) 2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXSafed  <Shared high level code used in the other modules internally.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXSafek% verismith.Function to show a bytestring in a hex format.& verismith@Converts unsafe list functions in the Prelude to a safe version.' verismithShow function for ( verismith8Inserts commas between '[Text]' and except the last one.) verismithEInserts commas and newlines between '[Text]' and except the last one.%&'()&'%()Result monadic type.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone =>?@AHVXq* verismithThe transformer for the - type. This- verismith#Result type which is equivalent to  or Error@. This is reimplemented so that there is full control over the ! definition and definition of a  transformer *. *+,-./0123 -./*+,012320Unsigned BitVec implementation.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXSafe245679y:G verismith^Specialisation of the above with Integer, so that infinitely large bit vectors can be stored.H verismithRBit Vector that stores the bits in an arbitrary container together with the size.L verismith,BitVecF construction, given width and value.M verismithBit selection. LSB is 0. verismithRotate bits in a H.GHIKJLMHIKJGLM$Definition of the Verilog AST types.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalNone245679=?@AHSVXDc verismith/The complete sourcetext for the Verilog module.f verismith'module'7 module_identifier [list_of_ports] ';' { module_item }  end_modulem verismith7Module item which is the body of the module expression.~ verismith4Local parameter that can be assigned anywhere using  localparam3. It cannot be changed by initialising the module. verismith:Parameter that can be assigned in blocks or modules using  parameter. verismithStatements in Verilog. verismithTime control (#NUM) verismithSequential block ( begin ... end) verismithblocking assignment (=) verismithNon blocking assignment (<=) verismith:Loop bounds shall be statically computable for a for loop. verismithQThis is currently a type because direct module declaration should also be added: #mod a(.y(y1), .x1(x11), .x2(x22));  verismith?Port declaration. It contains information about the type of the port, the size, and the port name. It used to also contain information about if it was an input or output port. However, this is not always necessary and was more cumbersome than useful, as a lot of ports can be declared without input and output port.This is now implemented inside f6 itself, which uses a list of output and input ports. verismith`Range that can be associated with any port or left hand side. Contains the msb and lsb bits as j. This means that they can be generated using parameters, which can in turn be changed at synthesis time. verismithCurrently, only wire and regO are supported, as the other net types are not that common and not a priority. verismith7Different port direction that are supported in Verilog. verismithInput direction for port (input). verismithOutput direction for port (output). verismithInout direction for port (inout). verismithcType that represents the left hand side of an assignment, which can be a concatenation such as in: {a, b, c} = 32'h94238;  verismithGConstant expression, which are known before simulation at compile time. verismithVerilog expression, which can either be a primary expression, unary expression, binary operator expression or a conditional expression. verismith>Number implementation containing the size and the value itself verismithSymbols verismith<Bit-wise concatenation of expressions represented by braces. verismith>Unary operators that are currently supported by the generator. verismith + verismith - verismith ! verismith ~ verismith & verismith ~& verismith | verismith ~| verismith ^ verismith ~^ verismith ^~ verismithHBinary operators that are currently supported in the verilog generation. verismith + verismith - verismith * verismith / verismith % verismith == verismith != verismith === verismith !== verismith && verismith || verismith < verismith <= verismith > verismith >=  verismith &  verismith |  verismith ^  verismith ^~  verismith ~^ verismith ** verismith << verismith >> verismith <<< verismith >>> verismith%Verilog syntax for an event, such as @x!, which is used for always blocks verismith;Verilog syntax for adding a delay, which is represented as #num. verismithIdentifier in Verilog. This is just a string of characters that can either be lowercase and uppercase for now. This might change in the future though, as Verilog supports many more characters in Identifiers.1 verismithtMay need to change this to Traversal to be safe. For now it will fail when the main has not been properly set with.2 verismithtMay need to change this to Traversal to be safe. For now it will fail when the main has not been properly set with."_`abcdefghijklmnopqrstuvwxyz{|}~      !"# !"#$%&'()*+,-./012"_`abcde       !"#$%&'()*+,-.!"~fghijklmnopqrstuvwxyz{|}#1/02 Class of the simulator.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone48 verismithType synonym for a * that will be used throughout  Verismith. This has instances for  and MonadIO if the 3 it is parametrised with also has those instances.9 verismithSynthesiser type class.D verismithSimulation type class.G verismith Tool class.L verismithChecks what modules are present in the synthesised output, as some modules may have been inlined. This could be improved if the parser worked properly.M verismith,Uses sed to replace a string in a text file.N verismithThis is used because rename only renames the definitions of modules of course, so instead this just searches and replaces all the module names. This should find all the instantiations and definitions. This could again be made much simpler if the parser works.R verismith2Helper function to convert bytestrings to integers: verismithSynthesiser tool instance verismithRun information verismithdoes not return any valuesE verismithSimulator instance verismithRun information verismithInputs to simulate verismith=Returns the value of the hash at the output of the testbench.#2389:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWX#8JGHDEF9:;<=>?@ABCIKLMNOPQRSTUVWX23  Code generation for Verilog AST.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone2=?` verismith`` class which determines that source code is able to be generated from the data structure using a. This will be stored in $ and can then be processed further. verismithMap a 'Maybe Statement' to N. If it is 'Just statement', the generated statements are returned. If it is , then ;n is returned. verismith Convert the c type to  so that it can be rendered. verismith Generate the f for a module and convert it to . verismith6Generates a parameter list. Can only be called with a  list. verismith7Generates a localparam list. Can only be called with a  list. verismithGenerates the assignment for a . verismithGenerates the assignment for a ~. verismith Conversts  to K for the module list, which means it only generates a list of identifiers. verismith Generate the  description. verismith Convert the  type to . verismith Generate a m. verismithGenerate continuous assignment verismith Generate  to . verismithConvert  to . verismithConvert  to . verismithGenerate verilog code for an . verismithGenerates verilog code for a . verismith!Generate the verilog code for an .b verismith Render the  to . This is equivalent to .]^_`ab]^_`ab /Template file for different configuration files(c) 2019, Yann HerklotzGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone xyz{|}~ xyz{|}~ #XST (ise) simulator implementation.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone "Vivado Synthesiser implementation.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone7(QuartusLight synthesiser implementation.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone#Quartus synthesiser implementation.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone'The identity simulator and synthesiser.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNoneB1Evaluation of Verilog expressions and statements.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone verismith Evaluates a  using a context of  as input. verismithDApply a function to all the bitvectors. Would be fixed by having a  instance for a polymorphic . verismithThis probably could be implemented using some recursion scheme in the future. It would also be fixed by having a polymorphic expression type.Defaults and common functions.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone$ verismithCreate an empty module. verismith+Set a module name for a module declaration. verismith+Add a input port to the module declaration.$Functions to mutate the Verilog AST.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone=?+ verismithReturn if the  is in a f. verismith_Find the last assignment of a specific wire/reg to an expression, and returns that expression. verismith]Transforms an expression by replacing an Identifier with an expression. This is used inside  and  traverseExpr to replace the  recursively. verismith5Replaces the identifier recursively in an expression. verismith Nest expressions for a specific  . If the ' is not found, the AST is not changed.This could be improved by instead of only using the last assignment to the wire that one finds, to use the assignment to the wire before the current expression. This would require a different approach though. verismithEReplaces an identifier by a expression in all the module declaration. verismithNest variables in the format w[0-9]* up to a certain number. verismith!Add a Module Instantiation using oq from the first module passed to it to the body of the second module. It first has to make all the inputs into reg.render $ instantiateMod m main module main; wire [(3'h4):(1'h0)] y; reg [(3'h4):(1'h0)] x; m m1(y, x); endmodule verismithtInstantiate without adding wire declarations. It also does not count the current instantiations of the same module.GenVerilog $ instantiateMod_ m m m(y, x); verismithtInstantiate without adding wire declarations. It also does not count the current instantiations of the same module.&GenVerilog $ instantiateModSpec_ "_" mm m(.y(y), .x(x)); verismith2Initialise all the inputs and outputs to a module.GenVerilog $ initMod mmodule m(y, x); output wire [(3'h4):(1'h0)] y; input wire [(3'h4):(1'h0)] x; endmodule verismithMake an 4 from and existing Identifier and an object with a  instance to make it unique. verismithcMake top level module for equivalence verification. Also takes in how many modules to instantiate. verismith/Make a top module with an assert that requires y_1 to always be equal to y_2<, which can then be proven using a formal verification tool. verismithqProvide declarations for all the ports that are passed to it. If they are registers, it should assign them to 0. verismith Simplify an  by using constants to remove  and simplify expressions. To make this work effectively, it should be run until no more changes were made to the expression.$GenVerilog . simplify $ (Id "x") + 0x+GenVerilog . simplify $ (Id "y") + (Id "x")(y + x) verismith Remove all 0 that do not appeare in the input list from an %. The identifier will be replaced by 1'b0., which can then later be simplified further.-GenVerilog . removeId ["x"] $ Id "x" + Id "y" (x + (1'h0))Yosys simulator implementation.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone.%Configuration file format and parser.(c) 2019, Yann HerklotzGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNonek-  verismith[[synthesiser]]_: description of the synthesis tool. There can be multiple of these sections in a config file. verismithname,: type of the synthesis tool. Can either be yosys, quartus,  quartuslight, vivado, xst. verismithbin(: location of the synthesis tool binary. verismith description9: description that should be used for the synthesis tool. verismithoutput": name of the output Verilog file. verismithDescription of the simulator verismithcommit+: the hash of the commit that was compiled. verismithversion-: the version of Verismith that was compiled. verismith [property],: properties for the generated Verilog file. verismithsize$: the size of the generated Verilog. verismithseedC: a possible seed that could be used to generate the same Verilog. verismithstatement.depth6: the maximum statement depth that should be reached. verismith module.depth4: the maximium module depth that should be reached. verismith module.maxN: the maximum number of modules that are allowed to be created at each level. verismith sample.methodb: the sampling method that should be used to generate specific distributions of random programs. verismith sample.size9: the number of samples to take for the sampling method. verismithoutput.combine8: if the output should be combined into one bit or not.  verismithnondeterminism\: the frequency at which nondeterminism should be generated (currently a work in progress).! verismith determinismg: the frequency at which determinism should be generated (currently modules are always deterministic)." verismith default.yosysK: Default location for Yosys, which will be used for equivalence checking.# verismith [probability]: combined probabilities.% verismithProbabilities for module items.& verismithProbabilities for statements.' verismithProbaiblities for expressions.( verismith/Probability of generating different statements.* verismithstatement.blocking1: probability of generating blocking assignments.+ verismithstatement.nonblocking4: probability of generating nonblocking assignments., verismithstatement.conditional5: probability of generating conditional statements (if statements).- verismithstatement.forloop&: probability of generating for loops.. verismithFProbability of generating different nodes inside a module declaration.0 verismithmoditem.assign: probability of generating an assign.1 verismithmoditem.sequential): probability of generating a sequential always block.2 verismithmoditem.combinational-: probability of generating an combinational always+ block. This is currently not implemented.3 verismithmoditem.instantiation4: probability of generating a module instantiation.4 verismith+Probability of different expressions nodes.6 verismith expr.number+: probability of generation a number like 4'ha. This should never be set to 0, as it is used as a fallback in case there are no viable identifiers, such as none being in scope.7 verismith expr.variableR: probability of generating an identifier that is in scope and of the right type.8 verismithexpr.rangeselect<: probability of generating a range selection from a port ( reg1[2:0]).9 verismith expr.unary-: probability of generating a unary operator.: verismith expr.binary.: probability of generation a binary operator.; verismith expr.ternary<: probability of generating a conditional ternary operator.< verismithexpr.concatenation,: probability of generating a concatenation.= verismith expr.stringe: probability of generating a string. This is not fully supported therefore currently cannot be set.> verismith expr.signed/: probability of generating a signed function  $signed(...).? verismith expr.unsigned2: probability of generating an unsigned function $unsigned(...).i      !"#$%&'()*+,-./0123456789:;<=>?RSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~i    {#$%&'456789:;<=>?./0123()*+,- !" vwxyzrstuefdVUWZRTSYX[\_]^`cabnmpoqkjgilh|}~NoneoV%%Icarus verilog module.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNonew verismithData directory. verismithIcarus simulator. verismithSynthesis tool to be tested. verismith#Original generated program to test. verismith=Test vectors to be passed as inputs to the generated Verilog. verismith'What the correct output should be. If @ is passed, then just return 'Pass ByteString' with the answer.%Simulator implementations.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNoney,:ET,E:T"Generate a report from a fuzz run.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNoneSXp  verismithiThe complete state that will be used during fuzzing, which contains the results from all the operations. verismith!Results of the equivalence check. verismithResults of the simulation. verismithResults of the synthesis step. verismithThe status of the synthesis using a simulator. This will be checked before attempting to run the equivalence checks on the simulator, as that would be unnecessary otherwise. verismithThe results of comparing the synthesised outputs of two files using a formal equivalence checker. This will either return a failure or an output which is most likely '()'. verismithtThe results from running a tool through a simulator. It can either fail or return a result, which is most likely a . verismith)Commont type alias for simulation results verismith'Common type alias for synthesis results verismith'Convert a description to a synthesiser.,,Various useful generators.(c) 2019, Yann HerklotzGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone>`) verismith Converts a  to an  by only keeping the  of the . verismith/Returns the probability from the configuration. verismith(Gets the current probabilities from the . verismith<Generates a random large number, which can also be negative. verismithRGenerates a random size for a wire so that it is not too small and not too large. verismith&Generates a random range by using the  and 0 as the lower bound. verismith#Generate a random bit vector using . verismithReturn a random . This currently excludes , 5 because they can take a long time to synthesis, and , ', because these are not synthesisable. u is also excluded because it can only be used in conjunction with base powers of 2 which is currently not enforced. verismithGenerate a random . verismithGenerate a random ! by using the current context of . verismithThe list of safe 8, meaning that these will not recurse and will end the  generation. verismithList of e that have the chance to recurse and will therefore not be used when the expression grows too large. verismith[Select a random port from a list of ports and generate a safe bit selection for that port. verismith&Generate a random expression from the A with a guarantee that it will terminate using the list of safe . verismithRuns a - for a random number of times, limited by an  that is passed to it. verismithzMake a new name with a prefix and the current nameCounter. The nameCounter is then increased so that the label is unique. verismith Makes a new  and then checks if the * already exists, if it does the existant 4 is returned, otherwise a new port is created with . This is used subsequently in all the functions to create a port, in case a port with the same name was already created. This could be because the generation is currently in the other branch of an if-statement. verismithYCreates a new port based on the current name counter and adds it to the current context. verismithCGenerates an expression from variables that are currently in scope. verismithZGenerates a random continuous assignment and assigns it to a random wire that is created. verismith7Generate a random assignment and assign it to a random . verismithGenerate a random . safely, by also increasing the depth counter. verismithGenerate a random conditional i. The nameCounter is reset between branches so that port names can be reused. This is safe because if a - is not reused, it is left at 0, as all the $ are initialised to 0 at the start. verismith~Generate a random for loop by creating a new variable name for the counter and then generating random statements in the body.  verismith Choose a  to generate.  verismithCGenerate a sequential always block which is dependent on the clock.  verismithShould resize a port that connects to a module port if the latter is larger. This should not cause any problems if the same net is used as input multiple times, and is resized multiple times, as it should only get larger.  verismithInstantiate a module, where the outputs are new nets that are created, and the inputs are taken from existing ports in the context.1 is subtracted from the inputs for the length because the clock is not counted and is assumed to be there, this should be made nicer by filtering out the clock instead. I think that in general there should be a special representation for the clock.  verismithGenerates a module instance by also generating a new module if there are not enough modules currently in the context. It keeps generating new modules for every instance and for every level until either the deepest level is achieved, or the maximum number of modules are reached.]If the maximum number of levels are reached, it will always pick an instance from the current context. The problem with this approach is that at the end there may be many more than the max amount of modules, as the modules are always set to empty when entering a new level. This is to fix recursive definitions of modules, which are not defined.oOne way to fix that is to also decrement the max modules for every level, depending on how many modules have already been generated. This would mean there would be moments when the module cannot generate a new instance but also not take a module from the current context. A fix for that may be to have a default definition of a simple module that is used instead.Another different way to handle this would be to have a probability of taking a module from a context or generating a new one. verismithGenerate a random module item. verismithEither return the + that was passed to it, or generate a new  based on the current . verismithGenerate a random ! by using the current context of  Parameters. verismithGenerate a random  and assign it to a constant expression which it will be initialised to. The assumption is that this constant expression should always be able to be evaluated with the current context of parameters. verismith<Evaluate a range to an integer, and cast it back to a range. verismithDCalculate a range to an int by maybe resizing the ranges to a value. verismithFilter out a port based on it's name instead of equality of the ports. This is because the ports might not be equal if the sizes are being updated. verismithWGenerates a module definition randomly. It always has one output port which is set to y. The size of y} is the total combination of all the locally defined wires, so that it correctly reflects the internal state of the module. verismith?Procedural generation method for random Verilog. Uses internal  and 5 to keep track of the current Verilog code structure. verismith Samples the  directly to generate random c using the 7 as the name of the main module and the configuration  to influence the generation. verismithGiven a  and a  will generate a _1 which has the top module set to the right name. verismithSampled and wrapped into a _ with the given top module name.(     (     Generate verilog from circuit.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone verismith Converts a  to an . verismith Converts a   to a ', which should be a bijective mapping. verismith^Generates the nested expression AST, so that it can then generate the assignment expressions. verismithyGenerate the continuous assignment AST for a particular node. If it does not have any nodes that link to it then return 8, as that means that the assignment will just be empty. Definition of the circuit graph.(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone   -Simple preprocessor for `define and comments.-(c) 2011-2015 Tom Hawkins, 2019 Yann HerklotzGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXSafe verismith:Remove comments from code. There is no difference between (* *) and * *$, therefore in this implementation, */ could close (*< and vice-versa, This will be fixed in an upcoming version. verismithA simple `define preprocessor.Tokens for Verilog parsing.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXSafe BY !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXZ[\]^BZ[Y !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWX\]^NoneF  verismithBEncode a Haskell String to a list of Word8 values, in UTF8 format.ee.Minimal Verilog parser to reconstruct the AST.(c) 2019, Yann HerklotzGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone  verismithXThis parser succeeds whenever the given predicate returns true when called with parsed Z . Same as &'. verismith Parses given . verismithParse without returning the . verismithgParse a Number depending on if it is in a hex or decimal form. Octal and binary are not supported yet. verismithTParses the ternary conditional operator. It will behave in a right associative way. verismithOTable of binary and unary operators that encode the right precedence for each. verismithbParse a range and return the total size. As it is inclusive, 1 has to be added to the difference. verismith Parses a  into cP by skipping any beginning whitespace and then parsing multiple Verilog source.m verismithParse a u containing verilog code. The parser currently only supports the subset of Verilog that is being generated randomly.m verismithName of parsed object. verismithContent to be parsed. verismithReturns $ with error message if parse fails.hijklmnomnoijklh +QuasiQuotation for verilog code in Haskell.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone#tq verismithhQuasiquoter for verilog, so that verilog can be written inline and be parsed to an AST at compile time.qq(<Verilog implementation with random generation and mutations.(c) 2019, Yann Herklotz GraveGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone&_`abcdefghijklmnopqrstuvwxyz{|}      !"#/0]^_amq_`abcdem]^_a      !"fghijklmnopqrstuvwxyz{|}#/0q!!Test case reducer implementation.(c) 2019, Yann HerklotzGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNoneSXVr verismithfReplacement type that supports returning different kinds of reduced replacements that could be tried. verismithSplit a list in two halves. verismithWhen given a Lens and a function that works on a lower replacement, it will go down, apply the replacement, and return a replacement of the original module.v verismith Deletes Id E if they are not part of the current scope, and replaces these by 0. verismithJChecks if a declaration is part of the current scope. If not, it returns  , otherwise y, as it should be kept. filterDecl :: [Identifier] -> ModItem -> Bool filterDecl ids (Decl Nothing (Port _ _ _ i) _) = i : ids filterDecl _ _ = TrueOChecks if a continuous assignment is in the current scope, if not, it returns . verismith'Remove all the undefined mod instances. verismithOClean all the undefined module instances in a specific module using a context. verismith2Check if a mod instance is in the current context. verismithAdds a f to a _.z verismith~Split a module declaration in half by trying to remove assign statements. This is only done in the main module of the source. verismith<Checks if a module item is needed in the module declaration. verismithSPretending that expr is an LVal for the case that it is in a module instantiation. verismithReturns the only identifiers that are directly tied to an expression. This is useful if one does not have to recurse deeper into the expressions.| verismithFClean a specific module. Have to be carful that the module is in the _, otherwise it will crash. verismith6Returns true if the text matches the name of a module.~ verismithRemoves half the modules randomly, until it reaches a minimal amount of modules. This is done by doing a binary search on the list of modules and removing the instantiations from the main module body. verismithReducer for module items. It does a binary search on all the module items, except assignments to outputs and input-output declarations. verismithQReduce expressions by splitting them in half and keeping the half that succeeds. verismith,Reduction using custom reduction strategies. verismith`Reduce an input to a minimal representation. It follows the reduction strategy mentioned above. verismith*Reduce using a script that is passed to it verismith Reduce a _ using two 9 that are passed to it. verismithFilepath for temporary file. verismithFailed or not. verismith#Input verilog source to be reduced. verismithReduced output.rstuvwxyz{|}~rstu~z{w|}yxv">Environment to run the simulator and synthesisers in a matrix.(c) 2019, Yann HerklotzGPL-3 yann [at] yannherklotz [dot] com experimentalPOSIXNone,>_K verismith}The main type for the fuzzing, which contains an environment that can be read from and the current state of all the results. verismith=Generate a specific number of random bytestrings of size 256. verismith?generates the specific number of bytestring with a random seed. verismithAlways reduces with respect to .# Verismith(c) 2018-2019, Yann HerklotzBSD-3 yann [at] yannherklotz [dot] com experimentalPOSIXNoneq verismith=Generate a specific number of random bytestrings of size 256. verismith?generates the specific number of bytestring with a random seed.  verismith-Randomly remove an option by setting it to 0. verismithWDraw a randomly generated DAG to a dot file and compile it to a png so it can be seen.  verismith.Function to show a bytestring in a hex format. verismith4Run a simulation on a random DAG or a random module.  verismithCode to be executed on a failure. Also checks if the failure was a timeout, as the timeout command will return the 124 error code if that was the case. In that case, the error will be moved to a different directory. verismithtRun a fuzz run and check if all of the simulators passed by checking if the generated Verilog files are equivalent. verismithGenerator for the Verilog file. verismith"Name of the folder on each thread. verismith&Name of the general folder being used. verismith Keep flag. verismithUsed to track the recursion. _`abcdefghijklmnopqrstuvwxyz{|}      !"#/0:ET]^_a      !"#$%&'()*+,-./0123456789:;<=>?RSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~mq._`ab ))*++,--./0123456789:;<=>?@ABBCDEFGHIJKLMNOOPQRSTUVWXYZ[\]^_`abcdefghijklkmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./012334556789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLM N O P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s s t u v w x y z { | } ~                                             c      !!"#$%&'()*+,--./011234566789:;;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[[\\]^_`abcdefghijklmno p!q!r!s!t!u!v!w!x!y!z!{!|!}!~!!!!!!!!!!!!!!!"""""""""""""""""""""""""""#####$$$$$$$$                  '!!!   ! ! !!!!!!"""####J#verismith-0.6.0.2-inplaceVerismith.Circuit.BaseVerismith.Circuit.InternalVerismith.Circuit.RandomVerismith.CounterEgVerismith.InternalVerismith.ResultVerismith.Verilog.BitVecVerismith.Verilog.ASTVerismith.Tool.InternalVerismith.Verilog.CodeGenVerismith.Tool.TemplateVerismith.Tool.XSTVerismith.Tool.VivadoVerismith.Tool.QuartusLightVerismith.Tool.QuartusVerismith.Tool.IdentityVerismith.Verilog.EvalVerismith.Verilog.InternalVerismith.Verilog.MutateVerismith.Tool.YosysVerismith.ConfigVerismith.OptParserVerismith.Tool.IcarusVerismith.ReportVerismith.GenerateVerismith.Circuit.GenVerismith.CircuitVerismith.Verilog.PreprocessVerismith.Verilog.TokenVerismith.Verilog.LexVerismith.Verilog.ParserVerismith.Verilog.QuoteVerismith.ReduceVerismith.Fuzz VerismithPaths_verismithVerismith.ToolText.Parsec.CharsatisfyVerismith.VerilogCEdgegetCEdgeCNodegetCNodeCircuit getCircuitGateAndOrXor $fRandomGate $fShowGate$fEqGate $fEnumGate $fBoundedGate $fOrdGatefromNodefilterGronlyinputsoutputsrDups rDupsCirc randomDAG genRandomDAG CounterEg_counterEgInitial_counterEgStatesparseCounterEg$fMonoidCounterEg$fSemigroupCounterEg $fEqCounterEg$fShowCounterEgshowBSsafeshowTcommacommaNLResultT runResultTResultFailPassjustPassjustFailannotate$fBifunctorResult$fMonadBaseResultResult $fMonadResult$fApplicativeResult$fFunctorResult$fMonoidResult$fSemigroupResult$fMonadShControlResultT$fMonadBaseControlIOResultT$fMonadTransControlResultT$fMonadTransResultT$fMonadBasebResultT$fMonadIOResultT$fMonadShResultT$fMonadResultT$fApplicativeResultT$fFunctorResultT $fEqResult $fShowResultBitVecBitVecFwidthvaluebitVecselect$fMonoidBitVecF$fSemigroupBitVecF$fFiniteBitsBitVecF $fBitsBitVecF$fIntegralBitVecF $fRealBitVecF $fNumBitVecF $fEnumBitVecF $fShowBitVecF $fEqBitVecF $fOrdBitVecF $fDataBitVecF$fFunctorBitVecF$fFoldableBitVecF$fTraversableBitVecF$fGenericBitVecF$fNFDataBitVecF SourceInfo_infoTop_infoSrcVerilog getVerilogModDecl_modId _modOutPorts _modInPorts _modItems _modParamsModItemModCAModInstInitialAlwaysDecl ParamDeclLocalParamDecl_modContAssign _modInstId _modInstName _modInstConns_declDir _declPort_declVal _paramDecl_localParamDecl LocalParam_localParamIdent_localParamValue Parameter _paramIdent _paramValue StatementTimeCtrl EventCtrlSeqBlock BlockAssignNonBlockAssign TaskEnable SysTaskEnable CondStmntForLoop _statDelay _statDStat _statEvent _statEStat _statements_stmntBA _stmntNBA _stmntTask _stmntSysTask_stmntCondExpr_stmntCondTrue_stmntCondFalse _forAssign_forExpr_forIncr _forStmnt ContAssign_contAssignNetLVal_contAssignExprAssign _assignReg _assignDelay _assignExprModConn ModConnNamed_modExpr _modConnNamePort _portType _portSigned _portSize _portNameRangerangeMSBrangeLSBPortTypeWireRegPortDirPortInPortOut PortInOutLValRegIdRegExprRegSize RegConcat_regId _regExprId_regExpr _regSizeId _regSizeRange_regConcTask _taskName _taskExpr ConstExprConstNumParamId ConstConcat ConstUnOp ConstBinOp ConstCondConstStr _constNum _constParamId _constConcat _constUnOp _constPrim _constLhs _constBinOp _constRhs _constCond _constTrue _constFalse _constStrExprNumberId VecSelect RangeSelectConcatUnOpBinOpCondApplStr UnaryOperatorUnPlusUnMinusUnLNotUnNotUnAndUnNandUnOrUnNorUnXorUnNxor UnNxorInvBinaryOperatorBinPlusBinMinusBinTimesBinDivBinModBinEqBinNEqBinCEqBinCNEqBinLAndBinLOrBinLTBinLEqBinGTBinGEqBinAndBinOrBinXorBinXNor BinXNorInvBinPowerBinLSLBinLSRBinASLBinASREventEIdEExprEAllEPosEdgeENegEdgeEOrECombDelay _getDelay Identifier getIdentifier constToExpr exprToConsttraverseModItem$fMonoidIdentifier$fSemigroupIdentifier$fIsStringIdentifier $fNumDelay$fPlatedConstExpr$fIsStringConstExpr$fMonoidConstExpr$fSemigroupConstExpr$fNumConstExpr $fNumRange $fPlatedExpr$fIsStringExpr $fMonoidExpr$fSemigroupExpr $fNumExpr$fIsStringLVal $fPlatedEvent$fMonoidStatement$fSemigroupStatement$fPlatedStatement$fMonoidVerilog$fSemigroupVerilog$fMonoidSourceInfo$fSemigroupSourceInfo$fEqIdentifier$fShowIdentifier$fOrdIdentifier$fDataIdentifier$fGenericIdentifier$fNFDataIdentifier $fEqDelay $fShowDelay $fOrdDelay $fDataDelay$fGenericDelay $fNFDataDelay$fEqBinaryOperator$fShowBinaryOperator$fOrdBinaryOperator$fDataBinaryOperator$fGenericBinaryOperator$fNFDataBinaryOperator$fEqUnaryOperator$fShowUnaryOperator$fOrdUnaryOperator$fDataUnaryOperator$fGenericUnaryOperator$fNFDataUnaryOperator $fEqConstExpr$fShowConstExpr$fOrdConstExpr$fDataConstExpr$fGenericConstExpr$fNFDataConstExpr $fEqPortDir $fShowPortDir $fOrdPortDir $fDataPortDir$fGenericPortDir$fNFDataPortDir $fEqPortType$fShowPortType $fOrdPortType$fDataPortType$fGenericPortType$fNFDataPortType $fEqRange $fShowRange $fOrdRange $fDataRange$fGenericRange $fNFDataRange$fEqExpr $fShowExpr $fOrdExpr $fDataExpr $fGenericExpr $fNFDataExpr$fEqLVal $fShowLVal $fOrdLVal $fDataLVal $fGenericLVal $fNFDataLVal$fEqTask $fShowTask $fOrdTask $fDataTask $fGenericTask $fNFDataTask $fEqEvent $fShowEvent $fOrdEvent $fDataEvent$fGenericEvent $fNFDataEvent$fEqPort $fShowPort $fOrdPort $fDataPort $fGenericPort $fNFDataPort $fEqModConn $fShowModConn $fOrdModConn $fDataModConn$fGenericModConn$fNFDataModConn $fEqAssign $fShowAssign $fOrdAssign $fDataAssign$fGenericAssign$fNFDataAssign$fEqContAssign$fShowContAssign$fOrdContAssign$fDataContAssign$fGenericContAssign$fNFDataContAssign $fEqStatement$fShowStatement$fOrdStatement$fDataStatement$fGenericStatement$fNFDataStatement $fEqParameter$fShowParameter$fOrdParameter$fDataParameter$fGenericParameter$fNFDataParameter$fEqLocalParam$fShowLocalParam$fOrdLocalParam$fDataLocalParam$fGenericLocalParam$fNFDataLocalParam $fEqModItem $fShowModItem $fOrdModItem $fDataModItem$fGenericModItem$fNFDataModItem $fEqModDecl $fShowModDecl $fOrdModDecl $fDataModDecl$fGenericModDecl$fNFDataModDecl $fEqVerilog $fShowVerilog $fOrdVerilog $fDataVerilog$fGenericVerilog$fNFDataVerilog$fEqSourceInfo$fShowSourceInfo$fOrdSourceInfo$fDataSourceInfo$fGenericSourceInfo$fNFDataSourceInfo constBinOp constConcat constCond constFalseconstLhsconstNum constParamId constPrimconstRhsconstStr constTrue constUnOptaskExprtaskNameregConcregExpr regExprIdregId regSizeId regSizeRangeportName portSignedportSizeportType modConnNamemodExpr assignDelay assignExpr assignRegcontAssignExprcontAssignNetLVal forAssignforExprforIncrforStmnt statDStat statDelay statEStat statEvent statementsstmntBA stmntCondExprstmntCondFalse stmntCondTruestmntNBA stmntSysTask stmntTaskdeclDirdeclPortdeclVallocalParamDecl modContAssign modInstConns modInstId modInstName paramDecl paramIdent paramValuelocalParamIdentlocalParamValuemodId modInPortsmodItems modOutPorts modParamsinfoSrcinfoTop$fWrappedVerilog$fRewrappedVerilogt$fWrappedIdentifier$fRewrappedIdentifiert$fWrappedDelay$fRewrappedDelayt_Initial_Always$fCorecursiveEvent$fRecursiveEvent$fFunctorEventF$fFoldableEventF$fTraversableEventF$fCorecursiveExpr$fRecursiveExpr$fFunctorExprF$fFoldableExprF$fTraversableExprF ConstExprF ConstNumFParamIdF ConstConcatF ConstUnOpF ConstBinOpF ConstCondF ConstStrF _constNumF_constParamIdF _constConcatF _constUnOpF _constPrimF _constLhsF _constBinOpF _constRhsF _constCondF _constTrueF _constFalseF _constStrF getModule getSourceIdaModule mainModule$fCorecursiveConstExpr$fRecursiveConstExpr$fFunctorConstExprF$fFoldableConstExprF$fTraversableConstExprFResultSh SynthesiserrunSynth synthOutputsetSynthOutputFailed EmptyFail EquivFail EquivErrorSimFail SynthFail TimeoutError SimulatorrunSimrunSimWithFileTooltoText renameSourceresultSh checkPresentcheckPresentModulesreplace replaceModsrootPathtimeouttimeout_bsToInoPrintlogger logCommand logCommand_executeexecute_$fMonoidFailed$fSemigroupFailed $fShowFailed $fEqFailed GenVerilog unGenVerilogSource genSourcerender$fSourceSourceInfo$fSourceVerilog$fSourceModDecl $fSourcePort$fSourcePortDir$fSourceModItem$fSourceContAssign $fSourceExpr$fSourceUnaryOperator $fSourceEvent $fSourceDelay $fSourceLVal$fSourceConstExpr$fSourcePortType$fSourceStatement $fSourceTask$fSourceIdentifier$fShowGenVerilog$fEqGenVerilog$fOrdGenVerilog$fDataGenVerilogyosysSynthConfigStdyosysSatConfigyosysSimConfigquartusLightSynthConfigquartusSynthConfigxstSynthConfigvivadoSynthConfig sbyConfigicarusTestbenchXSTxstBinxstDesc xstOutput defaultXST $fNFDataXST$fSynthesiserXST $fShowXST $fToolXST$fEqXSTVivado vivadoBin vivadoDesc vivadoOutput defaultVivado$fNFDataVivado$fSynthesiserVivado $fShowVivado $fToolVivado $fEqVivado QuartusLightquartusLightBinquartusLightDescquartusLightOutputdefaultQuartusLight$fNFDataQuartusLight$fSynthesiserQuartusLight$fShowQuartusLight$fToolQuartusLight$fEqQuartusLightQuartus quartusBin quartusDesc quartusOutputdefaultQuartus$fNFDataQuartus$fSynthesiserQuartus $fShowQuartus $fToolQuartus $fEqQuartusIdentity identityDescidentityOutputdefaultIdentity$fNFDataIdentity$fSynthesiserIdentity$fShowIdentity$fToolIdentity $fEqIdentity evaluateConstresizeregDeclwireDeclemptyMod setModName addModPort addModDecl testBench addTestBench defaultPort portToExprmodNameyPortwireregMutatemutExprinPort findAssignidTransnestId nestSourcenestUpToallVarsinstantiateModinstantiateMod_instantiateModSpec_ filterCharinitMod makeIdFrommakeTop makeTopAssert declareModsimplifyremoveIdcombineAssignscombineAssigns_fromPort$fMutateGenVerilog $fMutateMaybe $fMutate[]$fMutateSourceInfo$fMutateVerilog$fMutateModDecl$fMutateModItem$fMutateLocalParam$fMutateParameter$fMutateStatement$fMutateContAssign$fMutateAssign$fMutateModConn $fMutatePort $fMutateRange$fMutatePortType$fMutatePortDir $fMutateLVal $fMutateTask$fMutateConstExpr $fMutateExpr$fMutateUnaryOperator$fMutateBinaryOperator $fMutateEvent $fMutateDelay$fMutateIdentifierYosysyosysBin yosysDesc yosysOutput defaultYosys runEquivYosysrunEquiv $fNFDataYosys$fSynthesiserYosys $fShowYosys $fToolYosys $fEqYosysConfig _configInfo_configProbability_configProperty_configSimulators_configSynthesisersSynthDescription synthNamesynthBin synthDescsynthOutSimDescriptionsimName ConfProperty _propSize _propSeed_propStmntDepth _propModDepth_propMaxModules_propSampleMethod_propSampleSize _propCombine_propNonDeterminism_propDeterminism_propDefaultYosys Probability _probModItem _probStmnt _probExpr ProbStatement_probStmntBlock_probStmntNonBlock_probStmntCond _probStmntFor ProbModItem_probModItemAssign_probModItemSeqAlways_probModItemCombAlways_probModItemInstProbExpr _probExprNum _probExprId_probExprRangeSelect _probExprUnOp_probExprBinOp _probExprCond_probExprConcat _probExprStr_probExprSigned_probExprUnsigned $fEqProbExpr$fShowProbExpr$fEqProbModItem$fShowProbModItem$fEqProbStatement$fShowProbStatement$fEqProbability$fShowProbability$fEqConfProperty$fShowConfProperty$fEqInfo $fShowInfo$fEqSimDescription$fShowSimDescription$fEqSynthDescription$fShowSynthDescription $fEqConfig $fShowConfig probExprBinOpprobExprConcat probExprCond probExprId probExprNumprobExprRangeSelectprobExprSigned probExprStr probExprUnOpprobExprUnsignedprobModItemAssignprobModItemCombAlwaysprobModItemInstprobModItemSeqAlwaysprobStmntBlock probStmntCond probStmntForprobStmntNonBlockprobExpr probModItem probStmnt propCombinepropDefaultYosyspropDeterminismpropMaxModules propModDepthpropNonDeterminismpropSampleMethodpropSampleSizepropSeedpropSizepropStmntDepthconfigProbabilityconfigPropertyconfigSimulatorsconfigSynthesisersfromXST fromYosys fromVivado fromQuartusfromQuartusLight defaultConfigparseConfigFile parseConfig encodeConfigencodeConfigFile versionInfoOptsFuzzGenerateParseReduce ConfigOpt fuzzOutputfuzzConfigFile fuzzForced fuzzKeepAllfuzzNum fuzzNoSim fuzzNoEquivfuzzNoReductionfuzzExistingFilefuzzExistingFileTopfuzzCrossCheck fuzzCheckergenerateFilenamegenerateConfigFile parseFilenameparseTop parseOutputparseRemoveConstInConcatreduceFilename reduceTop reduceScriptreduceSynthesiserDesc reduceRerunconfigOptWriteConfigconfigOptConfigFileconfigOptDoRandomiseOptToolTYosysTXSTTIcarusopts $fShowOptToolIcarus icarusPathvvpPath defaultIcarusrunSimIc runSimIcEC$fNFDataIcarus$fSimulatorIcarus $fToolIcarus $fShowIcarus $fEqIcarus FuzzReport_fuzzDir _synthResults _simResults _synthStatus _fileLines _synthTime _equivTime _reducTime SynthStatus SynthResult SimResultSimTool IcarusSim SynthToolXSTSynth VivadoSynth YosysSynth QuartusSynthQuartusLightSynth IdentitySynthdefaultYosysSynthdefaultQuartusSynthdefaultQuartusLightSynthdefaultVivadoSynthdefaultXSTSynthdefaultIdentitySynthdefaultIcarusSim$fSynthesiserSynthTool$fToolSynthTool$fShowSynthTool$fNFDataSynthTool $fShowSimTool$fSimulatorSimTool $fToolSimTool$fNFDataSimTool$fShowSimResult$fShowSynthResult$fShowSynthStatus $fEqSynthTool $fEqSimTool $fEqSimResult$fEqSynthResult$fEqSynthStatus$fEqFuzzReport$fShowFuzzReport equivTime fileLinesfuzzDir reducTime simResults synthResults synthStatus synthTimedescriptionToSimdescriptionToSynthprintResultReport printSummary randomMod lvalFromPort probabilityaskProbabilitylargeNumwireSizerange genBitVecbinOpunOpconstExprWithContext exprSafeList exprRecListexprWithContextsomeImakeIdentifiernextPortnewPort scopedExpr contAssign assignmentseqBlock conditionalforLoop statement alwaysSeq resizePort instantiatemodInstmodItem moduleName constExpr parameter evalRange calcRange moduleDef procedural proceduralIO proceduralSrcproceduralSrcIO generateAST fromGraph uncomment preprocess TokenNameKWAliasKWAlways KWAlwaysComb KWAlwaysFf KWAlwaysLatchKWAndKWAssertKWAssignKWAssume KWAutomaticKWBeforeKWBeginKWBindKWBinsKWBinsofKWBitKWBreakKWBufKWBufif0KWBufif1KWByteKWCaseKWCasexKWCasezKWCell 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KWPackageKWPacked KWParameterKWPathpulseDollarKWPmos KWPosedge KWPrimitive KWPriority KWProgram KWProperty KWProtectedKWPull0KWPull1 KWPulldownKWPullupKWPulsestyleOneventKWPulsestyleOndetectKWPureKWRandKWRandc KWRandcaseKWRandsequenceKWRcmosKWReal KWRealtimeKWRefKWReg KWReleaseKWRepeatKWReturnKWRnmosKWRpmosKWRtran KWRtranif0 KWRtranif1 KWScalared KWSequence KWShortint KWShortrealKWShowcancelledKWSignedKWSmallKWSolve KWSpecify KWSpecparamKWStatic KWStrength0 KWStrength1KWString KWStrong0 KWStrong1KWStructKWSuper KWSupply0 KWSupply1KWTableKWTaggedKWTaskKWThis KWThroughoutKWTimeKWTimeprecision KWTimeunitKWTran KWTranif0 KWTranif1KWTriKWTri0KWTri1KWTriandKWTriorKWTriregKWType KWTypedef KWTypeOptionKWUnionKWUnique KWUnsignedKWUseKWVar KWVectored KWVirtualKWVoidKWWait KWWaitOrderKWWandKWWeak0KWWeak1KWWhile KWWildcardKWWireKWWithKWWithinKWWorKWXnorKWXorIdSimple IdEscapedIdSystemLitNumberUnsigned LitNumber LitString SymParenL SymParenR SymBrackL SymBrackR SymBraceL SymBraceRSymTildySymBangSymAtSymPound SymPercentSymHatSymAmpSymBarSymAsterSymDotSymCommaSymColonSymSemiSymEqSymLtSymGtSymPlusSymDash SymQuestionSymSlash SymDollar SymSQuote SymTildyAmp SymTildyBar SymTildyHat SymHatTildySymEqEq SymBangEq SymAmpAmp SymBarBar SymAsterAsterSymLtEqSymGtEqSymGtGtSymLtLt SymPlusPlus SymDashDash SymPlusEq SymDashEq SymAsterEq SymSlashEq SymPercentEqSymAmpEqSymBarEqSymHatEq SymPlusColon SymDashColon SymColonColon SymDotAster SymDashGt SymColonEq SymColonSlash SymPoundPoundSymBrackLAster SymBrackLEqSymEqGt SymAtAsterSymParenLAsterSymAsterParenR SymAsterGt SymEqEqEq SymBangEqEqSymEqQuestionEqSymBangQuestionEq SymGtGtGt SymLtLtLt SymLtLtEq SymGtGtEq SymBarDashGt SymBarEqGtSymBrackLDashGt SymAtAtParenLSymParenLAsterParenR SymDashGtGt SymAmpAmpAmp SymLtLtLtEq SymGtGtGtEqUnknownTokenPosition tokenString$fShowPosition $fEqPosition$fShowTokenName $fEqTokenName $fShowToken $fEqTokenalexScanTokens $fEqAlexPosn$fShowAlexPosnParser parseEventparseStatement parseModItem parseModDecl parseVerilogparseVerilogFileparseSourceInfoFile $fNumDecimalverilog ReplacementDualSingleNone filterExprclean takeReplaceremoveConstInConcat halveAssignsfindActiveWirescleanSourceInfocleanSourceInfoAll halveModules halveModItemshalveStatements halveExpr removeDeclreduce_reducereduceWithScript reduceSynthreduceSynthesis reduceSimIc$fTraversableReplacement$fFoldableReplacement$fApplicativeReplacement$fFunctorReplacement$fShowReplacement$fEqReplacementFuzzOpts_fuzzOptsOutput_fuzzOptsForced_fuzzOptsKeepAll_fuzzOptsIterations_fuzzOptsNoSim_fuzzOptsNoEquiv_fuzzOptsNoReduction_fuzzOptsConfig _fuzzDataDir_fuzzOptsCrossCheck_fuzzOptsChecker$fShowFuzzOpts $fEqFuzzOpts $fEqFuzzEnv $fShowFuzzEnv $fEqFuzzState$fShowFuzzStaterunFuzzmakepopfuzz fuzzInDir fuzzMultiple sampleSeed defaultMaindraw runSimulationrunEquivalence runReduceversion getBinDir getLibDir getDynLibDir getDataDir getLibexecDir getSysconfDirgetDataFileNamebaseGHC.Listfilterghc-prim GHC.TypesInt arbitraryEdge text-1.2.3.1Data.Text.InternalText Data.EitherEitherGHC.BaseMonad rotateBitVec#shelly-1.8.1-6XA3TPV3JpwEfifCViwJmf Shelly.LiftedMonadShdefMap GHC.MaybeNothing verilogSrc moduleDecl paramListNonEmptylocalParamList localParammodPortportportDir moduleItemexprbinaryOpunaryOpeventRecdelaylValIO System.IOputStrLnBindings applyBitVecFunctor"lens-4.17.1-94CX92SoGrtA1SZyH4fo01Control.Lens.Plated transformOfGHC.ShowShow _infoCommit _infoVersionbytestring-0.10.8.2Data.ByteString.Internal ByteStringBResultUResulttransformers-0.5.6.2 Control.Monad.Trans.State.StrictState rangeSelectContextStateGen nameCounter identElemControl.Monad.Trans.ReaderReader%hedgehog-1.0.1-Dm48LEnTzH93rSXLMzPRGuHedgehog.Internal.GenGenfrNodefromGate genAssignExprgenContAssignAST utf8Encodetoktok'parseNum parseCond parseTable parseRangeparseVerilogSrcStringhalvecombine filterAssignsFalseTrue Data.Foldableelem cleanModInst cleanModInst' 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